Datasheet

Data Sheet ADE7880
Rev. A | Page 83 of 104
REGISTERS LIST
Table 30. Registers Located in DSP Data Memory RAM
Address
Register
Name R/W
1
Bit
Length
Bit Length During
Communication
2
Type
3
Default Value Description
0x4380 AIGAIN R/W 24 32 ZPSE S 0x000000 Phase A current gain adjust.
0x4381 AVGAIN R/W 24 32 ZPSE S 0x000000 Phase A voltage gain adjust.
0x4382 BIGAIN R/W 24 32 ZPSE S 0x000000 Phase B current gain adjust.
0x4383 BVGAIN R/W 24 32 ZPSE S 0x000000 Phase B voltage gain adjust.
0x4384 CIGAIN R/W 24 32 ZPSE S 0x000000 Phase C current gain adjust.
0x4385 CVGAIN R/W 24 32 ZPSE S 0x000000 Phase C voltage gain adjust.
0x4386 NIGAIN R/W 24 32 ZPSE S 0x000000 Neutral current gain adjust.
0x4387 Reserved R/W 24 32 ZPSE S 0x000000 This location should not be written for proper
operation.
0x4388 DICOEFF R/W 24 32 ZPSE S 0x0000000 Register used in the digital integrator algorithm.
If the integrator is turned on, it must be set at
0xFF8000. In practice, it is transmitted as
0xFFF8000.
0x4389 APGAIN R/W 24 32 ZPSE S 0x000000 Phase A power gain adjust.
0x438A AWATTOS R/W 24 32 ZPSE S 0x000000 Phase A total active power offset adjust.
0x438B BPGAIN R/W 24 32 ZPSE S 0x000000 Phase B power gain adjust.
0x438C BWATTOS R/W 24 32 ZPSE S 0x000000 Phase B total active power offset adjust.
0x438D CPGAIN R/W 24 32 ZPSE S 0x000000 Phase C power gain adjust.
0x438E CWATTOS R/W 24 32 ZPSE S 0x000000 Phase C total active power offset adjust.
0x438F AIRMSOS R/W 24 32 ZPSE S 0x000000 Phase A current rms offset.
0x4390 AVRMSOS R/W 24 32 ZPSE S 0x000000 Phase A voltage rms offset.
0x4391 BIRMSOS R/W 24 32 ZPSE S 0x000000 Phase B current rms offset.
0x4392 BVRMSOS R/W 24 32 ZPSE S 0x000000 Phase B voltage rms offset.
0x4393 CIRMSOS R/W 24 32 ZPSE S 0x000000 Phase C current rms offset.
0x4394 CVRMSOS R/W 24 32 ZPSE S 0x000000 Phase C voltage rms offset.
0x4395 NIRMSOS R/W 24 32 ZPSE S 0x000000 Neutral current rms offset.
0x4396-
0x4397
Reserved N/A N/A N/A N/A 0x000000 These memory locations should not be written for
proper operation.
0x4398 HPGAIN R/W 24 32 ZPSE S 0x000000 Harmonic powers gain adjust.
0x4399 ISUMLVL R/W 24 32 ZPSE S 0x000000 Threshold used in comparison between the sum
of phase currents and the neutral current.
0x439A-
0x439E
Reserved N/A N/A N/A N/A 0x000000 These memory locations should not be written for
proper operation.
0x439F VLEVEL R/W 24 32 ZPSE S 0x000000 Register used in the algorithm that computes the
fundamental active and reactive powers.
0x43A0-
0x43A1
Reserved N/A N/A N/A N/A 0x000000 These memory locations should not be written for
proper operation.
0x43A2 AFWATTOS R/W 24 32 ZPSE S 0x000000 Phase A fundamental active power offset adjust.
0x43A3 BFWATTOS R/W 24 32 ZPSE S 0x000000 Phase B fundamental active power offset adjust.
0x43A4 CFWATTOS R/W 24 32 ZPSE S 0x000000 Phase C fundamental active power offset adjust.
0x43A5 AFVAROS R/W 24 32 ZPSE S 0x000000 Phase A fundamental reactive power offset adjust.
0x43A6 BFVAROS R/W 24 32 ZPSE S 0x000000 Phase B fundamental reactive power offset adjust.
0x43A7 CFVAROS R/W 24 32 ZPSE S 0x000000 Phase C fundamental reactive power offset adjust.
0x43A8 AFIRMSOS R/W 24 32 ZPSE S 0x000000 Phase A fundamental current rms offset.
0x43A9 BFIRMSOS R/W 24 32 ZPSE S 0x000000 Phase B fundamental current rms offset.
0x43AA CFIRMSOS R/W 24 32 ZPSE S 0x000000 Phase C fundamental current rms offset.
0x43AB AFVRMSOS R/W 24 32 ZPSE S 0x000000 Phase A fundamental voltage rms offset.
0x43AC BFVRMSOS R/W 24 32 ZPSE S 0x000000 Phase B fundamental voltage rms offset.
0x43AD CFVRMSOS R/W 24 32 ZPSE S 0x000000 Phase C fundamental voltage rms offset.
0x43AE HXWATTOS R/W 24 32 ZPSE S 0x000000 Active power offset adjust on harmonic X
(see
Harmonics Calculations section for details).
0x43AF HYWATTOS R/W 24 32 ZPSE S 0x000000 Aactive power offset adjust on harmonic Y
(see
Harmonics Calculations section for details).