Datasheet

ADE7880 Data Sheet
Rev. A | Page 8 of 104
t
F
t
F
t
HD;DAT
t
HD;STA
t
HIGH
t
SU;STA
t
SU;DAT
t
F
t
HD;STA
t
SP
t
SU;STO
t
F
t
BUF
t
LOW
SDA
SCLK
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
10193-002
Figure 2. I
2
C-Compatible Interface Timing
Table 3. SPI Interface Timing Parameters
Parameter Symbol Min Max Unit
SS to SCLK Edge
t
SS
50 ns
SCLK Period 0.4 4000
1
s
SCLK Low Pulse Width t
SL
175 ns
SCLK High Pulse Width t
SH
175 ns
Data Output Valid After SCLK Edge t
DAV
100 ns
Data Input Setup Time Before SCLK Edge t
DSU
100 ns
Data Input Hold Time After SCLK Edge t
DHD
5 ns
Data Output Fall Time t
DF
20 ns
Data Output Rise Time t
DR
20 ns
SCLK Rise Time t
SR
20 ns
SCLK Fall Time t
SF
20 ns
MISO Disable After SS Rising Edge
t
DIS
200 ns
SS High After SCLK Edge
t
SFS
0 ns
1
Guaranteed by design.
MSB LSB
LSB IN
INTERMEDIATE BITS
INTERMEDIATE BITS
t
SFS
t
DIS
t
SS
t
SL
t
DF
t
SH
t
DHD
t
DAV
t
DSU
t
SR
t
SF
t
DR
MSB IN
MOSI
MISO
SCLK
SS
10193-003
Figure 3. SPI Interface Timing