Datasheet
Data Sheet ADE7880
Rev. A | Page 71 of 104
CHECKSUM REGISTER
The ADE7880 has a checksum 32-bit register, CHECKSUM, that
ensures the configuration registers maintain their desired value
during Normal Power Mode PSM0.
The registers covered by this register are MASK0, MASK1,
COMPMODE, gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, HSDC_CFG,
all registers located in the DSP data memory RAM between
Address 0x4380 and Address 0x43BE and another eight 8-bit
reserved internal registers that always have default values. The
ADE7880 computes the cyclic redundancy check (CRC) based
on the IEEE802.3 standard. The registers are introduced one-by-
one into a linear feedback shift register (LFSR) based generator
starting with the least significant bit (as shown in Figure 96).
The 32-bit result is written in the CHECKSUM register. After
power-up or a hardware/software reset, the CRC is computed
on the default values of the registers giving a result equal to
0xAFFA63B9.
Figure 97 shows how the LFSR works: the MASK0, MASK1,
COMPMODE, Gain, CFMODE, CF1DEN, CF2DEN, CF3DEN,
CONFIG, MMODE, ACCMODE, LCYCMODE, and HSDC_CFG
registers, the registers located between Address 0x4380, and
Address 0x43BE and the eight 8-bit reserved internal registers
form the bits [a
2271
, a
2270
,…, a
0
] used by LFSR. Bit a
0
is the least
significant bit of the first register to enter LFSR; Bit a
2271
is the
most significant bit of the last register to enter LFSR. The
formulas that govern LFSR are as follows:
• b
i
(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that
form the CRC. Bit b
0
is the least significant bit, and Bit b
31
is the most significant.
• g
i
, i = 0, 1, 2, …, 31 are the coefficients of the generating
polynomial defined by the IEEE802.3 standard as follows:
G(x) = x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+
x
5
+ x
4
+ x
2
+ x + 1 (52)
g
0
= g
1
= g
2
= g
4
= g
5
= g
7
= 1
g
8
= g
10
= g
11
= g
12
= g
16
= g
22
= g
26
= 1 (53)
All of the other g
i
coefficients are equal to 0.
FB(j) = a
j – 1
XOR b
31
(j − 1) (54)
b
0
(j) = FB(j) AND g
0
(55)
b
i
(j) = FB(j) AND g
i
XOR b
i – 1
(j – 1), i = 1, 2, 3, ..., 31 (56)
Equation 54, Equation 55, and Equation 56 must be repeated for
j = 1, 2, …, 2272. The value written into the CHECKSUM register
contains the Bit b
i
(2272), i = 0, 1, …, 31.
Every time a configuration register of the ADE7880 is written or
changes value inadvertently, the Bit 25 (CRC) in STATUS1 register
is set to 1 to signal CHECKSUM value has changed. If Bit 25 (CRC)
in MASK1 register is set to 1, then the
IRQ1
interrupt pin is driven
low and the status flag CRC in STATUS1 is set to 1. The status bit is
cleared and the
IRQ1
pin is set to high by writing to the STATUS1
register with the status bit set to 1.
When Bit CRC in STATUS1 is set to 1 without any register
being written, it can be assumed that one of the registers has
changed value and therefore, the ADE7880 has changed
configuration. The recommended response is to initiate a
hardware/software reset that sets the values of all registers to the
default, including the reserved ones, and then reinitialize the
configuration registers.
2
271 0
LFSR
GENERATOR
ARRAY OF 2272 BITS
10193-071
Figure 96. CHECKSUM Register Calculation
b
0
LFSR
FB
g
0
g
1
g
2
g
31
b
1
g
3
b
2
b
31
a
1767
,
a
1766
,....,
a
2
,
a
1
,
a
0
10193-072
Figure 97. LFSR Generator Used in CHECKSUM Register Calculation