Datasheet

Data Sheet ADE7880
Rev. A | Page 7 of 104
Parameter
1, 2
Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY For specified performance
PSM0 Mode
VDD Pin 2.97 3.63 V Minimum = 3.3 V − 10%; maximum =
3.3 V + 10%
I
DD
25 28 mA
PSM1 and PSM2 Modes
VDD Pin 2.4 3.7 V
I
DD
PSM1 Mode 5.3 5.8 mA
PSM2 Mode 0.2 0.27 mA
PSM3 Mode For specified performance
VDD Pin 2.4 3.7 V
I
DD
in PSM3 Mode 1.8 6 A
1
See the Typical Performance Characteristics section.
2
See the Terminology section for a definition of the parameters.
3
⎥
⎦
⎤
⎢
⎣
⎡
L
f
2800
means the whole number of the division.
4
The CLKIN/CLKOUT load capacitors refer to the capacitors that are mounted between the CLKIN and CLKOUT pins of the ADE7880 and AGND. The capacitors should
be chosen based on the crystal manufacturer’s data sheet specification, and they must not have more than the maximum value specified in the table.
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, T
MIN
to T
MAX
= −40°C to +85°C. Note that dual
function pin names are referenced by the relevant function only within the timing tables and diagrams (see the Pin Configuration and
Function Descriptions section for full pin mnemonics and descriptions).
Table 2. I
2
C-Compatible Interface Timing Parameter
Standard Mode Fast Mode
Parameter Symbol Min Max Min Max Unit
SCL Clock Frequency f
SCL
0 100 0 400 kHz
Hold Time (Repeated) Start Condition t
HD;STA
4.0 0.6 s
Low Period of SCL Clock t
LOW
4.7 1.3 µs
High Period of SCL Clock t
HIGH
4.0 0.6 µs
Set-Up Time for Repeated Start Condition t
SU;STA
4.7 0.6 µs
Data Hold Time t
HD;DAT
0 3.45 0 0.9 µs
Data Setup Time t
SU;DAT
250 100 ns
Rise Time of Both SDA and SCL Signals t
R
1000 20 300 ns
Fall Time of Both SDA and SCL Signals t
F
300 20 300 ns
Setup Time for Stop Condition t
SU;STO
4.0 0.6 µs
Bus Free Time Between a Stop and Start Condition t
BUF
4.7 1.3 µs
Pulse Width of Suppressed Spikes t
SP
N/A
1
50 ns
1
N/A means not applicable.