Datasheet

ADE7880 Data Sheet
Rev. A | Page 6 of 104
Parameter
1, 2
Min Typ Max Unit Test Conditions/Comments
WAVEFORM SAMPLING Sampling CLKIN/2048, 16.384 MHz/2048 =
8 kSPS
Current and Voltage Channels
See the
Waveform Sampling Mode
section
Signal-to-Noise Ratio, SNR 72 dB PGA = 1
Signal-to-Noise-and-Distortion Ratio,
SINAD
72 dB PGA = 1
Bandwidth (−3 dB) 3.3 kHz
TIME INTERVAL BETWEEN PHASES
Measurement Error 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on
CF1, CF2, CF3 PULSE OUTPUTS
Maximum Output Frequency 68.818 kHz WTHR = VARTHR = VATHR = 3
Duty Cycle 50 % If CF1, CF2, or CF3 frequency > 6.25 Hz and
CFDEN is even and > 1
(1 + 1/CFDEN) ×
50
% If CF1, CF2, or CF3 frequency > 6.25 Hz and
CFDEN is odd and > 1
Active Low Pulse Width 80 ms If CF1, CF2, or CF3 frequency < 6.25 Hz
Jitter 0.04 % For CF1, CF2, or CF3 frequency = 1 Hz and
nominal phase currents are larger than
10% of full scale
REFERENCE INPUT
REF
IN/OUT
Input Voltage Range 1.1 1.3 V Minimum = 1.2 V − 8%; maximum =
1.2 V + 8%
Input Capacitance 10 pF
ON-CHIP REFERENCE Nominal 1.21 V at the REF
IN/OUT
pin at
T
A
= 25°C
PSM0 and PSM1 Modes
Reference Error ±2 mV
Output Impedance 1 kΩ
Temperature Coefficient 10 50 ppm/°C
CLKIN All specifications CLKIN of 16.384 MHz
Input Clock Frequency 16.22 16.384 16.55 MHz
Crystal Equivalent Series Resistance 30 200 Ω
CLKIN Load Capacitor
4
20 40 pF
CLKOUT Load Capacitor
4
20 40 pF
LOGIC INPUTS—MOSI/SDA, SCLK/SCL,
SS
,
RESET
, PM0, AND PM1
Input High Voltage, V
INH
2.4 V VDD = 3.3 V ± 10%
Input Current, I
IN
82 nA Input = VDD = 3.3 V
Input Low Voltage, V
INL
0.8 V VDD = 3.3 V ± 10%
Input Current, I
IN
−7.3 µA Input = 0, VDD = 3.3 V
Input Capacitance, C
IN
10 pF
LOGIC OUTPUTS—
IRQ0
,
IRQ1
, AND
MISO/HSD
VDD = 3.3 V ± 10%
Output High Voltage, V
OH
3.0 V VDD = 3.3 V ± 10%
I
SOURCE
800 µA
Output Low Voltage, V
OL
0.4 V VDD = 3.3 V ± 10%
I
SINK
2 mA
CF1, CF2, CF3/HSCLK
Output High Voltage, V
OH
2.4 V VDD = 3.3 V ± 10%
I
SOURCE
500 µA
Output Low Voltage, V
OL
0.4 V VDD = 3.3 V ± 10%
I
SINK
2 mA