Datasheet

ADE7880 Data Sheet
Rev. A| Page 102 of 104
Table 54. HCONFIG Register (Address 0xE900)
Bit Mnemonic Default Value Description
0 HRCFG 0
When this bit is cleared to 0, the bit 19 (HREADY) interrupt in MASK0 register is triggered
after a certain delay period. The delay period is set by bits HSTIME. The update frequency
after the settling time is determined by bits HRATE.
When this bit is set to 1, the bit 19 (HREADY) interrupt in MASK0 register is triggered starting
immediately after the harmonic calculations block has been setup. The update frequency is
determined by bits HRATE.
2:1 HPHASE 00 These bits decide what phase or neutral is analyzed by the harmonic calculations block.
00 = Phase A voltage and current.
01 = Phase B voltage and current.
10 = Phase C voltage and current.
11 = neutral current.
4:3 HSTIME 01
These bits decide the delay period after which, if HRCFG bit is set to 1, bit 19 (HREADY)
interrupt in MASK0 register is triggered.
00 = 500 ms.
01 = 750 ms.
10 = 1000 ms.
11 = 1250 ms.
7:5 HRATE 000 These bits manage the update rate of the harmonic registers.
000 = 125 µsec (8 kHz rate).
001 = 250 µsec (4 kHz rate).
010 = 1 ms (1 kHz rate).
011 = 16 ms (62.5 Hz rate).
100 = 128 ms (7.8125 Hz rate).
101 = 512 ms (1.953125 Hz rate).
110 = 1.024 sec (0.9765625 Hz rate).
111 = harmonic calculations disabled.
9:8 ACTPHSEL 00 These bits select the phase voltage used as time base for harmonic calculations.
00 = Phase A voltage.
01 = Phase B voltage.
10 = Phase C voltage.
11 = reserved. If selected, phase C voltage is used.
15:10 Reserved 0 Reserved. These bits do not manage any functionality.
Table 55. LPOILVL Register (Address 0xEC00)
Bit Mnemonic Default Value Description
2:0 LPOIL[2:0] 111 Threshold is put at a value corresponding to full scale multiplied by LPOIL/8.
7:3 LPLINE[4:0] 00000 The measurement period is (LPLINE + 1)/50 seconds.
Table 56. CONFIG2 Register (Address 0xEC01)
Bit Mnemonic Default Value Description
0 EXTREFEN 0 When this bit is 0, it signifies that the internal voltage reference is used in the ADCs.
When this bit is 1, an external reference is connected to the Pin 17 REF
IN/OUT
.
1 I2C_LOCK 0
When this bit is 0, the SS
/HSA pin can be toggled three times to activate the SPI port. If I
2
C is the
active serial port, this bit must be set to 1 to lock it in. From this moment on, toggling of the SS
/HSA pin and an eventual switch into using the SPI port is no longer possible. If SPI is the active serial
port, any write to CONFIG2 register locks the port. From this moment on, a switch into using I
2
C
port is no longer possible. Once locked, the serial port choice is maintained when the
changes PSMx power modes.
ADE7880
7:2 Reserved 0 Reserved. These bits do not manage any functionality.