Datasheet

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Polyphase Multifunction Energy Metering IC

with Harmonic Monitoring

Data Sheet

ADE7880

Rev. A

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FEATURES

Highly accurate; supports IEC 62053-21, IEC 62053-22,

IEC 62053-23, EN 50470-1, EN 50470-3, ANSI C12.20, and

IEEE1459 standards

Supports IEC 61000-4-7 Class I and Class II accuracy

specification

Compatible with 3-phase, 3- or 4-wire (delta or wye), and

other 3-phase services

Supplies rms, active, reactive and apparent powers, power

factor, THD, and harmonic distortion of all harmonics

within 2.8 kHz pass band on all phases

Supplies rms and harmonic distortions of all harmonics

within 2.8 kHz pass band on neutral current

Less than 1% error in harmonic current and voltage rms,

harmonic active and reactive powers over a dynamic

range of 2000 to 1 at T

= 25°C

Supplies total (fundamental and harmonic) active and

apparent energy and fundamental active/reactive energy

on each phase and on the overall system

Less than 0.1% error in active and fundamental reactive

energy over a dynamic range of 1000 to 1 at T

= 25°C

Less than 0.2% error in active and fundamental reactive

energy over a dynamic range of 5000 to 1 at T

= 25°C

Less than 0.1% error in voltage and current rms over a

dynamic range of 1000 to 1 at T

= 25°C

Battery supply input for missing neutral operation

Wide-supply voltage operation: 2.4 V to 3.7 V

Reference: 1.2 V (drift 10 ppm/°C typical) with external

overdrive capability

40-lead lead frame chip scale package (LFCSP), Pb-free, pin-

for-pin compatible with ADE7854, ADE7858, ADE7868 and

ADE7878

APPLICATIONS

Energy metering systems

Power quality monitoring

Solar inverters

Process monitoring

Protective devices

GENERAL DESCRIPTION

The ADE7880

is high accuracy, 3-phase electrical energy

measurement IC with serial interfaces and three flexible pulse

outputs. The ADE7880 device incorporates

second-order sigma-

delta (Σ-∆) analog-to-digital converters (ADCs), a digital

integrator, reference circuitry, and all of the signal processing

required to perform the total (fundamental and harmonic) active,

and apparent energy measurements, rms calculations, as well as

fundamental-only active and reactive energy measurements. In

addition, the ADE7880 computes the rms of harmonics on the

phase and neutral currents and on the phase voltages, together

with the active, reactive and apparent powers, and the power

factor and harmonic distortion on each harmonic for all phases.

Total harmonic distortion (THD) is computed for all currents

and voltages. A fixed function digital signal processor (DSP)

executes this signal processing. The DSP program is stored in

the internal ROM memory.

The ADE7880 is suitable for measuring active, reactive, and

apparent energy in various 3-phase configurations, such as wye

or delta services with, both, three and four wires. The ADE7880

provides system calibration features for each phase, that is, rms

offset correction, phase calibration, and gain calibration. The

CF1, CF2, and CF3 logic outputs provide a wide choice of

power information: total active powers, apparent powers, or the

sum of the current rms values, and fundamental active and

reactive powers.

The ADE7880 contains waveform sample registers that allow

access to all ADC outputs. The devices also incorporate power

quality measurements, such as short duration low or high

voltage detections, short duration high current variations, line

voltage period measurement, and angles between phase voltages

and currents. Two serial interfaces, SPI and I

C, can be used to

communicate with the ADE7880. A dedicated high speed

interface, the high speed data capture (HSDC) port, can be used

in conjunction with I

C to provide access to the ADC outputs

and real-time power information. The ADE7880 also has two

interrupt request pins,

IRQ0

and

IRQ1

, to indicate that an enabled

interrupt event has occurred. Three specially designed low power

modes ensure the continuity of energy accumulation when the

is in a tampering situation. The is available

in the 40-lead LFCSP, Pb-free package, pin-for-pin compatible

with , , , and devices.

ADE7880 ADE7880

ADE7854 ADE7858 ADE7868 ADE7878

Patents Pending.

Summary of content (104 pages)

PAGE 1
Data Sheet Polyphase Multifunction Energy Metering IC with Harmonic Monitoring ADE7880 FEATURES GENERAL DESCRIPTION Highly accurate; supports IEC 62053-21, IEC 62053-22, IEC 62053-23, EN 50470-1, EN 50470-3, ANSI C12.
PAGE 2
ADE7880 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Changing Phase Voltage Data path.......................................... 30 Applications....................................................................................... 1 Power Quality Measurements................................................... 31 General Description .........................................................................
PAGE 3
Data Sheet ADE7880 FUNCTIONAL BLOCK DIAGRAM RESET REFIN/OUT VDD AGND AVDD DVDD DGND 4 17 26 25 24 5 6 AIRMSOS LDO LDO 27 CLKOUT 28 ADE7880 APGAIN X2 CLKIN 27 AIRMS LPF 1.
PAGE 4
ADE7880 Data Sheet SPECIFICATIONS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter 1 , 2 ACTIVE ENERGY MEASUREMENT Active Energy Measurement Error (per Phase) Total Active Energy Fundamental Active Energy Min Typ Unit Test Conditions/Comments 0.1 % 0.2 % 0.1 % 0.2 % 0.1 % 0.2 % 0.1 % 0.
PAGE 5
Data Sheet Parameter 1 , 2 Output Frequency Variation Fundamental Reactive Energy Measurement Bandwidth (−3 dB) RMS MEASUREMENTS I RMS and V RMS Measurement Bandwidth (−3 dB) I RMS and V RMS Measurement Error (PSM0 Mode) MEAN ABSOLUTE VALUE (MAV) MEASUREMENT I MAV Measurement Bandwidth (PSM1 Mode) I MAV Measurement Error (PSM1 Mode) HARMONIC MEASUREMENTS Bandwidth (−3 dB) No attenuation Pass Band Fundamental Line Frequency fL ADE7880 Min Typ 0.01 3.3 Max 3.3 kHz 0.1 % 260 Hz 0.5 % 3.3 2.
PAGE 6
ADE7880 Parameter 1 , 2 WAVEFORM SAMPLING Data Sheet Min Typ Max Unit Current and Voltage Channels Signal-to-Noise Ratio, SNR Signal-to-Noise-and-Distortion Ratio, SINAD Bandwidth (−3 dB) TIME INTERVAL BETWEEN PHASES Measurement Error CF1, CF2, CF3 PULSE OUTPUTS Maximum Output Frequency Duty Cycle Active Low Pulse Width Jitter REFERENCE INPUT REFIN/OUT Input Voltage Range 72 72 dB dB 3.3 kHz 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on 68.818 50 kHz % (1 + 1/CFDEN) × 50 80 0.
PAGE 7
Data Sheet Parameter 1 , 2 POWER SUPPLY PSM0 Mode VDD Pin IDD PSM1 and PSM2 Modes VDD Pin IDD PSM1 Mode PSM2 Mode PSM3 Mode VDD Pin IDD in PSM3 Mode 1 2 3 4 ADE7880 Min Typ Max Unit Test Conditions/Comments For specified performance 3.63 V Minimum = 3.3 V − 10%; maximum = 3.3 V + 10% 28 mA 3.7 V 5.3 0.2 5.8 0.27 mA mA 1.8 3.7 6 V μA 2.97 25 2.4 For specified performance 2.4 See the Typical Performance Characteristics section.
PAGE 8
ADE7880 Data Sheet SDA tSU;DAT tF tF tLOW tHD;STA tSP tBUF tF tF SCLK tHD;DAT tSU;STO tSU;STA tHIGH START CONDITION REPEATED START CONDITION 10193-002 tHD;STA STOP START CONDITION CONDITION Figure 2. I2C-Compatible Interface Timing Table 3.
PAGE 9
Data Sheet ADE7880 Table 4. HSDC Interface Timing Parameter Parameter HSA to HSCLK Edge HSCLK Period HSCLK Low Pulse Width HSCLK High Pulse Width Data Output Valid After HSCLK Edge Data Output Fall Time Data Output Rise Time HSCLK Rise Time HSCLK Fall Time HSD Disable After HSA Rising Edge HSA High After HSCLK Edge Symbol tSS Min 0 125 50 50 tSL tSH tDAV tDF tDR tSR tSF tDIS tSFS Max 40 20 20 10 10 5 0 HSA tSS tSFS HSCLK tSL tSF tSR tDIS MSB INTERMEDIATE BITS LSB tDF tDR Figure 4.
PAGE 10
ADE7880 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
PAGE 11
Data Sheet ADE7880 40 39 38 37 36 35 34 33 32 31 NC SS/HSA MOSI/SDA MISO/HSD SCLK/SCL CF3/HSCLK CF2/HREADY CF1 IRQ1 NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 ADE7880 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 NC IRQ0 CLKOUT CLKIN VDD AGND AVDD VAP VBP NC NOTES 1. NC = NO CONNECT. 2. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE PAD ON THE PCB TO CONFER MECHANICAL STRENGTH TO THE PACKAGE.
PAGE 12
ADE7880 Data Sheet Pin No. 18, 19, 22, 23 Mnemonic VN, VCP, VBP, VAP 24 AVDD 25 AGND 26 VDD 27 CLKIN 28 CLKOUT 29, 32 IRQ0, IRQ1 33, 34, 35 CF1, CF2/HREADY, CF3/HSCLK 36 SCLK/SCL 37 38 39 EP MISO/HSD MOSI/SDA SS/HSA Exposed Pad Description Analog Inputs for the Voltage Channel. This channel is used with the voltage transducer and is referenced as the voltage channel in this data sheet. These inputs are single-ended voltage inputs with a maximum signal level of ±0.
PAGE 13
Data Sheet ADE7880 0.5 0.5 0.3 0.3 0.1 0.1 ERROR (%) –0.1 –0.3 1 10 100 Figure 7. Total Active Energy Error as Percentage of Reading (Gain = +1, Power Factor = 1) over Temperature with Internal Reference and Integrator Off 100 0.3 0.1 –0.1 –0.3 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) –0.5 0.01 10193-101 –0.5 0.01 Figure 8. Total Active Energy Error as Percentage of Reading over Gain with Internal Reference and Integrator Off +85°C, PF = 1.0 +25°C, PF = 1.
PAGE 14
ADE7880 0.1 –0.1 1 10 100 0.5 0.3 –0.1 –0.3 1 10 100 Figure 14. Fundamental Active Energy Error as Percentage of Reading (Gain = +1) over Power Supply with Internal Reference and Integrator Off GAIN = +1 GAIN = +2 GAIN = +4 GAIN = +8 GAIN = +16 0.1 –0.1 –0.5 0.01 1 10 100 Figure 17. Fundamental Reactive Energy Error as Percentage of Reading over Gain with Internal Reference and Integrator Off 0.5 0.5 0.3 0.3 0.1 0.1 –0.1 0.
PAGE 15
Data Sheet 0.3 0.1 0.1 ERROR (%) –0.1 –0.1 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) –0.5 0.01 10193-112 –0.5 0.01 –0.3 GAIN ERROR (% ERROR RELATIVE TO FUNDAMENTAL) ERROR (%) 10 100 5 0.3 0.1 –0.1 –0.3 0.1 1 10 100 Figure 20. Fundamental Reactive Energy Error as Percentage of Reading (Gain = +16) over Temperature with Internal Reference and Integrator On 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 10193-113 +85°C, PF = 1.0 +25°C, PF = 1.0 –40°C, PF = 1.
PAGE 16
ADE7880 Data Sheet 4 2 0 –2 –4 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 25. Harmonic I RMS Error as Percentage of Reading (Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading, 750 ms Settling Time, 125 μs Update Rate –4 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) Figure 28. Harmonic Reactive Power Error as Percentage of Reading (Gain = +1), 51 Harmonics, 55 Hz Fundamental, Single Reading, 750 ms Settling Time, 125 μs Update Rate –2 –4 0.
PAGE 17
Data Sheet ADE7880 4 2 0 –2 –4 –6 0.01 0.1 1 10 100 PERCENTAGE OF FULL-SCALE CURRENT (%) 10193-124 MEASUREMENT ERROR (% of Reading) 6 Figure 31. Harmonic Apparent Power Error as Percentage of Reading (Gain = +1), 51 Harmonics, 55 Hz Fundamental, 10 Averages per Reading, 750 ms Settling Time, 125 μs Update Rate Rev.
PAGE 18
ADE7880 Data Sheet TEST CIRCUIT 3.3V 10kΩ 1µF 1kΩ 5 10nF MISO/HSD 37 SAME AS IAP, IAN 10nF 13 ICP CF3/HSCLK 35 ADE7880 14 ICN 1.5kΩ 6 25 4.7µF + 0.1µF 16.384MHz CLKIN 27 20pF 10193-007 23 VAP 20pF CLKOUT 28 AGND 22 VBP SAME AS CF2 IRQ0 29 REFIN/OUT 17 DGND SAME AS VCP SAME AS VCP CF1 33 IRQ1 32 19 VCP 10nF 10kΩ CF2/HREADY 34 18 VN 1kΩ 3.3V SCLK/SCL 36 9 IBP 12 IBN 0.
PAGE 19
Data Sheet ADE7880 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7880 is defined by Measurement Error = Energy Registered by ADE 7880 − True Energy × 100% (1) True Energy Phase Error Between Channels The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current and the voltage channel.
PAGE 20
ADE7880 Data Sheet POWER MANAGEMENT The ADE7880 has four modes of operation, determined by the state of the PM0 and PM1 pins (see Table 8). These pins provide complete control of the ADE7880 operation and can easily be connected to an external microprocessor I/O. The PM0 and PM1 pins have internal pull-up resistors. See Table 10 and Table 11 for a list of actions that are recommended before and after setting a new power mode. Table 8.
PAGE 21
Data Sheet ADE7880 into Sleep Mode PSM3. If the IRQ1 pin is triggered low at the end of the measurement period, this signifies that at least one current input is above the defined threshold and current is flowing through the system, although no voltage is present at the ADE7880 pins.
PAGE 22
ADE7880 Data Sheet Table 11.
PAGE 23
Data Sheet ADE7880 POWER-UP PROCEDURE 3.3V – 10% 2.0V ± 10% ADE7880 PSM0 READY 0V ADE7880 POWERED UP POR TIMER TURNED ON 40ms MICROPROCESSOR MAKES THE ADE7880 MICROPROCESSOR RSTDONE CHOICE BETWEEN INTERRUPT I2C AND SPI ENTER PSM3 SETS ADE7880 TRIGGERED IN PSM0 10193-009 26ms Figure 34. Power-Up Procedure The ADE7880 contains an on-chip power supply monitor that supervises the power supply (VDD). At power-up, until VDD reaches 2 V ± 10%, the chip is in an inactive state.
PAGE 24
ADE7880 Data Sheet HARDWARE RESET SOFTWARE RESET FUNCTIONALITY The ADE7880 has a RESET pin. If the ADE7880 is in PSM0 mode and the RESET pin is set low, then the ADE7880 enters the hardware reset state. The ADE7880 must be in PSM0 mode for a hardware reset to be considered. Setting the RESET pin low while the ADE7880 is in PSM1, PSM2, and PSM3 modes does not have any effect. Bit 7 (SWRST) in the CONFIG register manages the software reset functionality in PSM0 mode. The default value of this bit is 0.
PAGE 25
Data Sheet ADE7880 THEORY OF OPERATION DIFFERENTIAL INPUT V1 + V2 = 500mV MAX PEAK ANALOG INPUTS COMMON MODE VCM = ±25mV MAX V1 + V2 +500mV V1 IAP, IBP, ICP, OR INP V2 IAN, IBN, ICN, OR INN VCM –500mV 10193-010 VCM Figure 35. Maximum Input Level, Current Channels, Gain = 1 All inputs have a programmable gain amplifier (PGA) with a possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and IC inputs is set in Bits[2:0] (PGA1[2:0]) of the Gain register.
PAGE 26
ADE7880 Data Sheet sampling frequency, that is, 1.024 MHz, move into the band of interest for metering, that is, 40 Hz to 3.3 kHz. To attenuate the high frequency (near 1.024 MHz) noise and prevent the distortion of the band of interest, a low-pass filter (LPF) must be introduced. For conventional current sensors, it is recommended to use one RC filter with a corner frequency of 5 kHz for the attenuation to be sufficiently high at the sampling frequency of 1.024 MHz.
PAGE 27
Data Sheet ADE7880 ZX SIGNAL DATA RANGE ZX DETECTION LPF1 0x514791 = +5,326,737 CURRENT PEAK, OVERCURRENT DETECT 0V PGA1 BITS REFERENCE GAIN[2:0] ×1, ×2, ×4, ×8, ×16 AIGAIN[23:0] HPFEN BIT CONFIG3[0] IAP VIN PGA1 CURRENT RMS (IRMS) CALCULATION INTEN BIT CONFIG[0] DSP ADC IAWV WAVEFORM SAMPLE REGISTER DIGITAL INTEGRATOR 0xAEB86F = –5,326,737 TOTAL/FUNDAMENTAL ACTIVE AND REACTIVE POWER CALCULATION HPF IAN CURRENT CHANNEL DATA RANGE AFTER INTEGRATION CURRENT CHANNEL DATA RANGE +0.
PAGE 28
ADE7880 Data Sheet The waveform samples of the current channel are taken at the output of HPF and stored in the 24-bit signed registers, IAWV, IBWV, ICWV, and INWV at a rate of 8 kSPS. All power and rms calculations remain uninterrupted during this process. Bit 17 (DREADY) in the STATUS0 register is set when the IAWV, IBWV, ICWV, and INWV registers are available to be read using the I2C or SPI serial port.
PAGE 29
Data Sheet ADE7880 signed register is accessed as a 32-bit register with four MSBs padded with 0s and sign extended to 28 bits, which practically means it is transmitted equal to 0x0FFF8000. –20 –25 –30 30 35 40 45 50 55 FREQUENCY (Hz) 60 65 When the digital integrator is switched off, the ADE7880 can be used directly with a conventional current sensor, such as a current transformer (CT).
PAGE 30
ADE7880 Data Sheet Voltage Waveform Gain Registers CHANGING PHASE VOLTAGE DATA PATH There is a multiplier in the signal path of each phase voltage. The voltage waveform can be changed by ±100% by writing a corresponding twos complement number to the 24-bit signed voltage waveform gain registers (AVGAIN, BVGAIN, and CVGAIN). For example, if 0x400000 is written to those registers, the ADC output is scaled up by 50%. To scale the input by −50%, write 0xC00000 to the registers.
PAGE 31
Data Sheet ADE7880 cleared and the IRQ1 pin is set to high by writing to the STATUS1 register with the status bit set to 1. POWER QUALITY MEASUREMENTS Zero-Crossing Detection The ADE7880 has a zero-crossing (ZX) detection circuit on the phase current and voltage channels. The neutral current data path does not contain a zero-crossing detection circuit. Zerocrossing events are used as a time base for various power quality measurements and in the calibration process.
PAGE 32
ADE7880 Data Sheet The phase sequence error detection circuit is functional only when the ADE7880 is connected in a 3-phase, 4-wire, three voltage sensors configuration (Bits[5:4], CONSEL[1:0] in the ACCMODE register, set to 00). In all other configurations, only two voltage sensors are used; therefore, it is not recommended to use the detection circuit. In these cases, use the time intervals between phase voltages to analyze the phase sequence (see the Time Interval Between Phases section for details).
PAGE 33
Data Sheet ADE7880 256 kHz) for 60 Hz systems. The delays between phase voltages or phase currents are used to characterize how balanced the load is. The delays between phase voltages and currents are used to compute the power factor on each phase as shown in the following Equation 6: ⎡ 360o × f LINE ⎤ cosφx = cos ⎢ ANGLEx × ⎥ 256 kHz ⎦ ⎣ (6) in STATUS1 register is set to 1 to indicate the condition and the bit VSPHASE[0] in the PHSTATUS register is set back to 0.
PAGE 34
ADE7880 Data Sheet IPPHASE/VPPHASE BITS 2. 3. 4. 5. 27 26 25 24 23 00000 Enable SAG interrupts in the MASK1 register by setting Bit 16 (SAG) to 1. When a SAG event happens, the IRQ1 interrupt pin goes low and Bit 16 (SAG) in the STATUS1 is set to 1. The STATUS1 register is read with Bit 16 (SAG) set to 1. The PHSTATUS register is read, identifying on which phase or phases a SAG event happened. The STATUS1 register is written with Bit 16 (SAG) set to 1. Immediately, the SAG bit is erased.
PAGE 35
Data Sheet ADE7880 register is set to 1. To find the phase that triggered the interrupt, one of either the IPEAK or VPEAK registers is read immediately after reading the STATUS1 register. Next, the status bits are cleared, and the IRQ1 pin is set to high by writing to the STATUS1 register with the status bit set to 1. Note that the internal zero-crossing counter is always active.
PAGE 36
ADE7880 Data Sheet In 3-phase systems, the neutral current is equal to the algebraic sum of the phase currents IN(t) = IA(t) + IB(t) + IC(t) If there is a mismatch between these two quantities, then a tamper situation may have occurred in the system. The ADE7880 computes the sum of the phase currents adding the content of the IAWV, IBWV, and ICWV registers, and storing the result into the ISUM 28-bit signed register: ISUM(t) = IA(t) + IB(t) + IC(t).
PAGE 37
Data Sheet ADE7880 Figure 63 illustrates how the phase compensation is used to remove x = −1° phase lead in IA of the current channel from the external current transducer (equivalent of 55.5 μs for 50 Hz systems). To cancel the lead (1°) in the current channel of Phase A, a phase lead must be introduced into the corresponding voltage channel. Using Equation 8, APHCAL is 57 least significant bits, rounded up from 56.8. The phase lead is achieved by introducing a time delay of 55.
PAGE 38
ADE7880 Data Sheet REFERENCE CIRCUIT The nominal reference voltage at the REFIN/OUT pin is 1.2 ± 0.075% V. This is the reference voltage used for the ADCs in the ADE7880. The REFIN/OUT pin can be overdriven by an external source, for example, an external 1.2 V reference. The voltage of the ADE7880 reference drifts slightly with temperature; see the Specifications section for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part.
PAGE 39
Data Sheet • • ADE7880 If the ADE7880 registers located in the data memory RAM have not been modified, write 0x0001 into the Run register to start the DSP. If the ADE7880 registers located in the data memory RAM have to be modified, first execute a software or a hardware reset, initialize all ADE7880 registers at desired values, enable the write protection and then write 0x0001 into the Run register to start the DSP.
PAGE 40
ADE7880 Data Sheet the integrator is enabled, that is, when Bit 0 (INTEN) in the CONFIG register is set to 1, the equivalent rms value of a fullscale sinusoidal signal at 50 Hz is 3,759,718 (0x395E66) and at 60 Hz is 3,133,207 (0x2FCF17). Table 12. Settling Time for I RMS Measurement The accuracy of the current rms is typically 0.1% error from the full-scale input down to 1/1000 of the full-scale input when PGA = 1. Additionally, this measurement has a bandwidth of 3.3 kHz.
PAGE 41
Data Sheet ADE7880 212000 Current RMS Offset Compensation 211500 211000 210500 210000 LSB The ADE7880 incorporates a current rms offset compensation register for each phase: AIRMSOS, BIRMSOS, CIRMSOS, and NIRMSOS. These are 24-bit signed registers that are used to remove offsets in the current rms calculations. An offset can exist in the rms calculation due to input noises that are integrated in the dc component of I2(t).
PAGE 42
ADE7880 Data Sheet Voltage Channel RMS Calculation this measurement has a bandwidth of 3.3 kHz. It is recommended to read the rms registers synchronous to the voltage zero crossings to ensure stability. The IRQ1 interrupt can be used to indicate when a zero crossing has occurred (see the Interrupts section). Figure 69 shows the detail of the signal processing chain for the rms calculation on one of the phases of the voltage channel.
PAGE 43
Data Sheet ADE7880 Voltage RMS Offset Compensation Total Active Power Calculation The ADE7880 incorporates voltage rms offset compensation registers for each phase: AVRMSOS, BVRMSOS, and CVRMSOS. These are 24-bit signed registers used to remove offsets in the voltage rms calculations. An offset can exist in the rms calculation due to input noises that are integrated in the dc component of V2(t). One LSB of the voltage rms offset compensation register is equivalent to one LSB of the voltage rms register.
PAGE 44
ADE7880 Data Sheet HPFEN BIT AIGAIN CONFIG3[0] INTEN BIT CONFIG[0] IA APGAIN HPF AVGAIN HPFEN BIT CONFIG3[0] INSTANTANEOUS PHASE A ACTIVE POWER LPF VA : HPF DIGITAL SIGNAL PROCESSOR 24 AWATT 10193-045 APHCAL AWATTOS LPSEL BIT CONFIG3[1] Figure 70.
PAGE 45
Data Sheet ADE7880 Fundamental Active Power Calculation The ADE7880 computes the fundamental active power using a proprietary algorithm that requires some initializations function of the frequency of the network and its nominal voltage measured in the voltage channel. Bit 14 (SELFREQ) in the COMPMODE register must be set according to the frequency of the network in which the ADE7880 is connected. If the network frequency is 50 Hz, clear this bit to 0 (the default value).
PAGE 46
ADE7880 Data Sheet Bits[8:6] (REVAPC, REVAPB, and REVAPA, respectively) in the STATUS0 register are set when a sign change occurs in the power selected by Bit 6 (REVAPSEL) in the ACCMODE register. PHSIGN register is read immediately after reading the STATUS0 register. Next, the status bit is cleared and the IRQ0 pin is returned to high by writing to the STATUS0 register with the corresponding bit set to 1.
PAGE 47
Data Sheet ADE7880 ⎧∞ ⎫ Energy = ∫ p (t )dt = Lim ⎨ ∑ p (nT ) × T ⎬ T→0 ⎩n=0 ⎭ The ADE7880 achieves the integration of the active power signal in two stages (see Figure 74). The process is identical for both total and fundamental active powers. The first stage accumulates the instantaneous phase total or fundamental active power at 1.024MHz, although they are computed by the DSP at 8 kHz rate.
PAGE 48
ADE7880 Data Sheet The active power is accumulated in each watt-hour accumulation 32-bit register (AWATTHR, BWATTHR, CWATTHR, AFWATTHR, BFWATTHR, and CFWATTHR) according to the configuration of Bit 5 and Bit 4 (CONSEL bits) in the ACCMODE register. The various configurations are described in Table 14. Table 14.
PAGE 49
Data Sheet ADE7880 ∞ set to high again by writing to the STATUS0 register with the corresponding bit set to 1. Because the active power is integrated on an integer number of half-line cycles in this mode, the sinusoidal components are reduced to 0, eliminating any ripple in the energy calculation.
PAGE 50
ADE7880 Data Sheet Fundamental Reactive Power Offset Calibration Table 16 presents the settling time for the fundamental reactive power measurement, which is the time it takes the power to reflect the value at the input of the ADE7880. The ADE7880 provides a fundamental reactive power offset register on each phase. The AFVAROS, BFVAROS, and CFVAROS registers compensate the offsets in the fundamental reactive power calculations.
PAGE 51
Data Sheet ADE7880 Sign of Fundamental Reactive Power Calculation Note that the fundamental reactive power is a signed calculation. Table 17 summarizes the relationship between the phase difference between the voltage and the current and the sign of the resulting reactive power calculation. The ADE7880 has sign detection circuitry for reactive power calculations that can monitor the fundamental reactive powers.
PAGE 52
ADE7880 Data Sheet On the ADE7880, the fundamental phase reactive powers are accumulated in the AFVARHR, BFVARHR, and CFVARHR 32bit signed registers. The reactive energy register content can roll over to full-scale negative (0x80000000) and continue increasing in value when the reactive power is positive. Conversely, if the reactive power is negative, the energy register underflows to full-scale positive (0x7FFFFFFF) and continues to decrease in value. Table 18.
PAGE 53
Data Sheet ADE7880 ZXSEL[0] IN LCYCMODE[7:0] power is by multiplying the voltage rms value by the current rms value (also called the arithmetic apparent power). ZEROCROSSING DETECTION (PHASE A) S = V rms × I rms ZXSEL[1] IN LCYCMODE[7:0] where: S is the apparent power. V rms and I rms are the rms voltage and current, respectively. LINECYC[15:0] ZEROCROSSING DETECTION (PHASE B) CALIBRATION CONTROL The ADE7880 computes the arithmetic apparent power on each phase.
PAGE 54
ADE7880 Data Sheet Apparent Power Gain Calibration The average apparent power result in each phase can be scaled by ±100% by writing to one of the phase’s PGAIN 24-bit registers (APGAIN, BPGAIN, or CPGAIN). Note that these registers are the same gain registers used to compensate the other powers computed by the ADE7880. See the Active Power Gain Calibration section for details on these registers.
PAGE 55
Data Sheet ADE7880 ZXSEL[0] IN LCYCMODE[7:0] by writing to the STATUS0 register with the corresponding bit set to 1. ZEROCROSSING DETECTION (PHASE A) Setting Bit 6 (RSTREAD) of the LCYCMODE register enables a read-with-reset for all xVAHR accumulation registers, that is, the registers are reset to 0 after a read operation. ZEROCROSSING DETECTION (PHASE B) Integration Time Under Steady Load The discrete time sample period for the accumulation register is 976.5625 ns (1.024 MHz frequency).
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ADE7880 Data Sheet ACTIVE (–) REACTIVE (–) PF (+) enabled on both the active and apparent energies. This is done by setting the xLWATT and xLVA bits in the LCYCMODE register (Address 0xE702). The update rate of the power factor measurement is now an integral number of half line cycles that can be programmed into the LINECYC register (Address 0xE60C).
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Data Sheet ADE7880 When the ADE7880 analyzes a phase, the following metering quantities are computed:    pf z  sgnQz   Fundamental phase current rms: I1 Fundamental phase voltage rms: V1 RMS of up to three harmonics of phase current: Ix, Iy, Iz, x,y,z=2, 3,…, N RMS of up to three harmonics of phase voltage: Vx, Vy, Vz, x,y,z=2, 3,…, N Fundamental phase active power P1 = V1I1cos(φ1 − γ1) Fundamental phase reactive power Q1 = V1I1sin(φ1 − γ1)   Fundamental phase apparent power S1 = V 1 I1 
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Data Sheet ADE7880 ACTPHSEL BITS HCONFIG[9,8] SELECT HPHASE BITS THE PHASE USED TO AS TIME BASE HCONFIG[2,1] SELECT THE PHASE BEING MONITORED IA, VA IB, VB ADE7880 HARMONIC CALCULATIONS IC, VC IN, ISUM HX, HY, HZ REGISTERS SELECT THE HARMONICS TO MONITOR OUTPUT REGISTERS USED WHEN ONE OF PHASES A, B, C IS ANALYZED FVRMS FIRMS FWATT FVAR FVA FPF VTHD ITHD HXVRMS HXIRMS HXWATT HXVAR HXVA HXPF HXVHD HXIHD HYVRMS HYIRMS HYWATT HYVAR HYVA HYPF HYVHD HYIHD HZVRMS HZIRMS HZWATT HZV
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Data Sheet ADE7880 Table 20.
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ADE7880 Data Sheet Table 21.
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Data Sheet ADE7880 HPHASE BITS HCONFIG[2, 1] SELECT THE PHASE BEING MONITORED AIRMSOS 27 BIRMSOS 27 FIRMS CIRMSOS HPHASE BITS HCONFIG[2, 1] SELECT THE GAIN BEING USED 27 FUNDAMENTAL COMPONENTS CALCULATIONS APGAIN OR BPGAIN OR CPGAIN HPHASE BITS HCONFIG[2, 1] SELECT THE PHASE BEING MONITORED FVA AVRMSOS 27 BVRMSOS 27 FVRMS CVRMSOS 10193-058 27 Figure 83.
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ADE7880 Data Sheet HXIRMSOS 27 HXIRMS HYIRMSOS 27 HYIRMS HZIRMSOS HARMONIC COMPONENTS CALCULATIONS 27 HZIRMS HXVRMSOS 27 HXVRMS HYVRMSOS 27 HYVRMS HXVRMSOS HZVRMS 10193-059 27 Figure 84.
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Data Sheet ADE7880 HXWATTOS 22 ÷ HPGAIN HYWATTOS 22 ÷ HARMONIC COMPONENTS CALCULATIONS HPGAIN HZWATTOS HXVAROS HYVAROS HZVAROS HXVAR 22 ÷ HPGAIN HZWATT 22 ÷ HPGAIN HYWATT 22 ÷ HPGAIN HXWATT HYVAR 22 ÷ HZVAR 10193-061 HPGAIN Figure 86. Harmonic Active and Reactive Powers Signal Processing The harmonic distortions of the three harmonic components are stored into the HXVHD, HXIHD, HYVHD, HYIHD, HZVHD, and HZIHD 24-bit registers in 3.21 signed format.
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ADE7880 Data Sheet to 750 ms, the settling time of the harmonic calculations. Other possible values are 500 ms (HSTIME = 00), 1 sec (10) and 1250 ms (11). The second approach, enabled when Bit 0 (HRCFG) of HCONFIG register is set to 1, sets Bit 19 (HREADY) in STATUS0 register to 1 every time the harmonic calculations are updated at the update frequency determined by HRATE bits without waiting for the harmonic calculations to settle.
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Data Sheet ADE7880 active, reactive, or apparent powers under steady load conditions. This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 87 illustrates the energy-to-frequency conversion in the ADE7880. The DSP computes the instantaneous values of all phase powers: total active, fundamental active, fundamental reactive, and apparent.
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ADE7880 Data Sheet By default, the TERMSELx bits are all 1 and the CF1SEL bits are 000, the CF2SEL bits are 100, and the CF3SEL bits are 010. This means that by default, the CF1 digital-to-frequency converter produces signals proportional to the sum of all 3-phase total active powers, CF2 produces signals proportional to fundamental reactive powers, and CF3 produces signals proportional to apparent powers.
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Data Sheet ADE7880 The CFx pulse output is active low and preferably connected to an LED, as shown in Figure 88. Bits[14:12] (CF3LATCH, CF2LATCH, and CF1LATCH) of the CFMODE register enable this process when set to 1. When cleared to 0, the default state, no latch occurs. The process is available even if the CFx output is not enabled by the CFxDIS bits in the CFMODE register. VDD CFx PIN 10193-063 Energy Registers and CF Outputs for Various Accumulation Modes Figure 88.
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ADE7880 Data Sheet converter. In this mode, the CFx pulses synchronize perfectly with the active energy accumulated in xWATTHR registers because the powers are accumulated in the same way in both data paths. Figure 92 shows how absolute active power accumulation works.
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Data Sheet ADE7880 energy accumulated into the accumulator reaches one of the WTHR, VARTHR, or VATHR thresholds, a dedicated interrupt can be triggered synchronously with the corresponding CFx pulse. The sign of each sum can be read in the PHSIGN register. REACTIVE ENERGY NO-LOAD THRESHOLD REACTIVE POWER NO-LOAD THRESHOLD indicate the sign of the sum of phase powers. When cleared to 0, the sum is positive. When set to 1, the sum is negative.
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ADE7880 Data Sheet The VANOLOAD register usually contains the same value as the APNOLOAD register. When APNOLOAD and VANOLOAD are set to 0x0, the no load detection circuit is disabled. If only VANOLOAD is set to 0, then the no load condition is triggered based only on the total active power being lower than APNOLOAD. In the same way, if only APNOLOAD is set to 0x0, the no load condition is triggered based only on the apparent power being lower than VANOLOAD.
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Data Sheet ADE7880 • CHECKSUM REGISTER The ADE7880 has a checksum 32-bit register, CHECKSUM, that ensures the configuration registers maintain their desired value during Normal Power Mode PSM0.
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ADE7880 Data Sheet INTERRUPTS The ADE7880 has two interrupt pins, IRQ0 and IRQ1. Each of the pins is managed by a 32-bit interrupt mask register, MASK0 and MASK1, respectively. To enable an interrupt, a bit in the MASKx register must be set to 1. To disable it, the bit must be cleared to 0. Two 32-bit status registers, STATUS0 and STATUS1, are associated with the interrupts.
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Data Sheet ADE7880 t1 t2 MCU INTERRUPT FLAG SET t3 PROGRAM SEQUENCE GLOBAL INTERRUPT MASK JUMP TO ISR CLEAR MCU INTERRUPT FLAG READ STATUSx WRITE BACK STATUSx ISR ACTION (BASED ON STATUSx CONTENTS) ISR RETURN GLOBAL INTERRUPT MASK RESET JUMP TO ISR 10193-073 IRQx Figure 98.
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ADE7880 Data Sheet I2C-Compatible Interface I2C Write Operation 2 The ADE7880 supports a fully licensed I C interface. The I C interface is implemented as a full hardware slave. SDA is the data I/O pin, and SCL is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on-chip SPI interface. The maximum serial clock frequency supported by this interface is 400 kHz.
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Data Sheet ADE7880 I2C Read Operation with the master generating a new start condition followed by an address byte. The most significant seven bits of this address byte constitute the address of the ADE7880, and they are equal to 0111000b. Bit 0 of the address byte is a read/write bit. Because this is a read operation, it must be set to 1; thus, the first byte of the read operation is 0x71. After this byte is received, the ADE7880 generates an acknowledge.
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ADE7880 Data Sheet The registers containing the harmonic calculation results are located starting at Address 0xE880 and are all 32-bit width. They can be read in two ways: one register at a time (see the I2C Read Operation section for details) or multiple consecutive registers at a time in a burst mode. This burst mode is accomplished in two stages.
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Data Sheet ADE7880 SS SCLK 15 14 0 0 0 0 0 0 0 1 REGISTER ADDRESS 31 30 MISO 1 0 10193-079 MOSI 1 0 REGISTER VALUE Figure 104. SPI Read Operation of a 32-Bit Register SS SCLK 0 0 0 0 0 0 0 1 REGISTER ADDRESS 31 0 REGISTER 0 VALUE MISO 31 0 REGISTER n VALUE 10193-080 MOSI Figure 105.
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ADE7880 Data Sheet SS SCLK MOSI 0 0 0 0 0 0 0 0 1 0 31 30 REGISTER ADDRESS 1 0 REGISTER VALUE 10193-081 15 14 Figure 106. SPI Write Operation of a 32-Bit Register HSDC Interface The high speed data capture (HSDC) interface is disabled after default. It can be used only if the ADE7880 is configured with an I2C interface. The SPI interface of ADE7880 cannot be used at the same time with HSDC. Bit 6 (HSDCEN) in the CONFIG register activates HSDC when set to 1.
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Data Sheet ADE7880 Figure 108 shows the HSDC transfer protocol for HGAP = 0, HXFER[1:0] = 00 and HSAPOL = 0. Note that the HSDC interface sets a data bit on the HSD line every HSCLK high-tolow transition and the value of Bit HSIZE is irrelevant. Figure 109 shows the HSDC transfer protocol for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0. Note that the HSDC interface introduces a seven-HSCLK cycles gap between every 32-bit word.
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ADE7880 Data Sheet HSCLK 31 0 IAVW (32-BIT) 31 7 HCLK CYCLES 0 VAWV (32-BIT) 31 0 31 IBWV (32-BIT) 7 HCLK CYCLES 0 CFVAR (32-BIT) 10193-084 HSDATA HSA Figure 109. HSDC Communication for HSIZE = 0, HGAP = 1, HXFER[1:0] = 00, and HSAPOL = 0 HSCLK 31 24 IAVW (BYTE 3) 23 7 HCLK CYCLES 16 IAVW (BYTE 2) 15 7 HCLK CYCLES IAVW (BYTE 1) 8 7 0 CFVAR (BYTE 0) 10193-085 HSDATA HSA Figure 110.
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Data Sheet ADE7880 SILICON ANOMALY This anomaly list describes the known issues with the ADE7880 silicon identified by the Version register (Address 0xE707) being equal to 1. Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended workarounds outlined here.
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ADE7880 Data Sheet Table 29. No Load Condition Does Not Function as Defined [er004, Version = 1 Silicon] Background Issue Workaround Related Issues Total active power no load uses the total active energy and the apparent energy to trigger the no load condition.
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Data Sheet ADE7880 REGISTERS LIST Table 30.
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ADE7880 Data Sheet Address 0x43B0 Register Name HZWATTOS R/W 1 R/W Bit Length 24 Bit Length During Communication 2 32 ZPSE Type 3 S Default Value 0x000000 0x43B1 HXVAROS R/W 24 32 ZPSE S 0x000000 0x43B2 HYVAROS R/W 24 32 ZPSE S 0x000000 0x43B3 HZVAROS R/W 24 32 ZPSE S 0x000000 0x43B4 HXIRMSOS R/W 24 32 ZPSE S 0x000000 0x43B5 HYIRMSOS R/W 24 32 ZPSE S 0x000000 0x43B6 HZIRMSOS R/W 24 32 ZPSE S 0x000000 0x43B7 HXVRMSOS R/W 24 32 ZPSE S 0x000000 0x43B8
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Data Sheet ADE7880 Table 32.
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ADE7880 Data Sheet Bit Length During Communication 2 32 SE 32 SE 32 SE 32 SE 32 SE Type 3 S S S S S Default Value 4 N/A N/A N/A N/A N/A Address 0xE50F 0xE510 0xE511 0xE512 0xE513 Register Name INWV VAWV VBWV VCWV AWATT R/W 1 R R R R R Bit Length 24 24 24 24 24 0xE514 BWATT R 24 32 SE S N/A 0xE515 CWATT R 24 32 SE S N/A 0xE516 to 0xE518 0xE519 Reserved R 24 32 SE S 0x000000 AVA R 24 32 SE S N/A 0xE51A BVA R 24 32 SE S N/A 0xE51B CVA R 24 32 SE S N/A 0xE51F CH
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Data Sheet ADE7880 Bit Length During Communication 2 Type 3 Default Value 4 Address Register Name R/W 1 Bit Length 0xE702 LCYCMODE R/W 8 8 U 0x78 0xE703 0xE704 0xE705 PEAKCYC SAGCYC CFCYC R/W R/W R/W 8 8 8 8 8 8 U U U 0x00 0x00 0x01 0xE706 0xE707 0xE7FD HSDC_CFG Version LAST_RWDATA8 R/W R R 8 8 8 8 8 8 U U U 0x00 0xE880 FVRMS R 24 32 S N/A 0xE881 FIRMS R 24 32 S N/A 0xE882 FWATT R 24 32 S N/A 0xE883 FVAR R 24 32 S N/A 0xE884 FVA R 24 32 S N/A 0
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ADE7880 Data Sheet Bit Length During Communication 2 Type 3 Default Value 4 Address Register Name R/W 1 Bit Length 0xE898 HZVRMS R 24 32 S N/A 0xE899 HZIRMS R 24 32 S N/A 0xE89A 0xE89B 0xE89C 0xE89D 0xE89E HZWATT HZVAR HZVA HZPF HZVHD R R R R R 24 24 24 24 24 32 32 32 32 32 S S S S S N/A N/A N/A N/A N/A 0xE89F HZIHD R 24 32 S N/A 0xE8A0 to 0xE8FF 0xE900 Reserved 24 32 HCONFIG R/W 16 16 U 0x08 0xE902 0xE903 0xE904 0xE905 0xE906 0xE907 0xE908 APF BPF CPF APERIOD
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Data Sheet ADE7880 R/W 1 Bit Length Bit Length During Communication 2 Type 3 Default Value 4 Address Register Name 0xEA0B to 0xEBFE 0xEBFF Reserved 8 8 Reserved 8 8 0xEC00 LPOILVL R/W 8 8 U 0x07 0xEC01 CONFIG2 R/W 8 8 U 0x00 Description computations. Reserved. These registers are always 0. This address can be used in manipulating the SS/HSA pin when SPI is chosen as the active port. See the Serial Interfaces section for details. Overcurrent threshold used during PSM2 mode.
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ADE7880 Data Sheet Bit 9 Mnemonic REVPSUM1 Default Value 0 10 REVFRPA 0 11 REVFRPB 0 12 REVFRPC 0 13 REVPSUM2 0 14 CF1 15 CF2 16 CF3 17 DREADY 0 18 REVPSUM3 0 19 HREADY 0 31:18 Reserved 0 0000 0000 0000 Description When this bit is set to 1, it indicates that the sum of all phase powers in the CF1 data path has changed sign. The sign itself is indicated in Bit 3 (SUM1SIGN) of the PHSIGN register (see Table 46).
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Data Sheet ADE7880 Table 37. STATUS1 Register (Address 0xE503) Bit 0 Mnemonic NLOAD Default Value 0 Description When this bit is set to 1, it indicates that at least one phase entered no load condition determined by the total active power and apparent power. The phase is indicated in Bits[2:0] (NLPHASE[x]) in the PHNOLOAD register (see Table 41.) When this bit is set to 1, it indicates that at least one phase entered no load condition based on fundamental active and reactive powers.
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ADE7880 Data Sheet Bit 24 Mnemonic PKV Default Value 0 25 CRC 0 31:26 Reserved 000 0000 Description When this bit is set to 1, it indicates that the period used to detect the peak value in the voltage channel has ended. VPEAK register contains the peak value and the phase where the peak has been detected (see Table 35). When this bit is set to 1, it indicates the ADE7880 has computed a different checksum relative to the one computed when the Run register was set to 1. Reserved.
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Data Sheet ADE7880 Bit 18 Mnemonic REVPSUM3 Default Value 0 19 HREADY 0 31:19 Reserved 00 0000 0000 0000 Description When this bit is set to 1, it enables an interrupt when the sum of all phase powers in the CF3 data path changes sign. When this bit is set to 1, it enables an interrupt when the harmonic block output registers have been updated. If Bit 1 (HRCFG) in HCONFIG register is cleared to 0, the interrupt is triggered every time the harmonic calculations are updated at 8 kHz rate.
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ADE7880 Data Sheet Bit 20 Mnemonic MISMTCH Default Value 0 22:21 23 Reserved PKI 00 0 24 PKV 0 25 CRC 0 31:26 Reserved 000 0000 Description When this bit is set to 1, it enables an interrupt when ISUM − INWV > ISUMLVL is greater than the value indicated in ISUMLVL register. Reserved. These bits do not manage any functionality. When this bit is set to 1, it enables an interrupt when the period used to detect the peak value in the current channel has ended.
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Data Sheet ADE7880 Bit 4 Mnemonic FNLPHASE[1] Default Value 0 5 FNLPHASE[2] 0 6 VANLPHASE[0] 0 7 VANLPHASE[1] 0 8 VANLPHASE[2] 0 15:9 Reserved 000 0000 Description 0: Phase B is out of no load condition based on fundamental active/reactive powers. 1: Phase B is in no load condition based on fundamental active/reactive powers. This bit is set together with Bit 1 (FNLOAD) in STATUS1. 0: Phase C is out of no load condition based on fundamental active/reactive powers.
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ADE7880 Data Sheet Table 43. Gain Register (Address 0xE60F) Bit 2:0 Mnemonic PGA1[2:0] Default Value 000 5:3 PGA2[2:0] 000 8:6 PGA3[2:0] 000 15:9 Reserved 000 0000 Description Phase currents gain selection. 000: gain = 1. 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 101, 110, 111: reserved. When set, the ADE7880 behaves like PGA1[2:0] = 000. Neutral current gain selection. 000: gain = 1. 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 101, 110, 111: reserved.
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Data Sheet ADE7880 Bit 8:6 Mnemonic CF3SEL[2:0] Default Value 010 Description 000: the CF3 frequency is proportional to the sum of total active powers on each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register. 010: the CF3 frequency is proportional to the sum of apparent powers on each phase identified by Bits[8:6] (TERMSEL3[x]) in the COMPMODE register.
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ADE7880 Data Sheet Bit 3 Mnemonic SUM1SIGN Default Value 0 4 AFVARSIGN 0 5 BFVARSIGN 0 6 CFVARSIGN 0 7 SUM2SIGN 0 8 SUM3SIGN 0 15:9 Reserved 000 0000 Description 0: if the sum of all phase powers in the CF1 data path is positive. 1: if the sum of all phase powers in the CF1 data path is negative. Phase powers in the CF1 data path are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by Bits[2:0] (CF1SEL[x]) of the CFMODE register.
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Data Sheet Bit 13:12 Mnemonic VTOIC[1:0] 15:14 Reserved ADE7880 Default Value 00 Description These bits decide what phase voltage is considered together with Phase C current in the power path. 00 = Phase C voltage. 01 = Phase A voltage. 10 = Phase B voltage. 11 = reserved. When set, the ADE7880 behaves like VTOIC[1:0] = 00. Reserved. Table 48.
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ADE7880 Data Sheet Bit 6 Mnemonic REVAPSEL Default Value 0 7 Reserved 1 Description 0: The total active power on each phase is used to trigger a bit in the STATUS0 register as follows: on Phase A triggers Bit 6 (REVAPA), on Phase B triggers Bit 7 (REVAPB), and on Phase C triggers Bit 8 (REVAPC).
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Data Sheet Bit 7 Mnemonic PFMODE ADE7880 Default Value 0 Description 0: power factor calculation uses instantaneous values of various phase powers used in its expression. 1: power factor calculation uses phase energies values calculated using line cycle accumulation mode. Bits LWATT and LVA in LCYCMODE register must be enabled for the power factors to be computed correctly.
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ADE7880 Data Sheet Table 54. HCONFIG Register (Address 0xE900) Bit 0 Mnemonic HRCFG Default Value 0 2:1 HPHASE 00 4:3 HSTIME 01 7:5 HRATE 000 9:8 ACTPHSEL 00 15:10 Reserved 0 Description When this bit is cleared to 0, the bit 19 (HREADY) interrupt in MASK0 register is triggered after a certain delay period. The delay period is set by bits HSTIME. The update frequency after the settling time is determined by bits HRATE.
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Data Sheet ADE7880 OUTLINE DIMENSIONS 0.30 0.23 0.18 31 40 30 0.50 BSC 1 TOP VIEW 0.80 0.75 0.70 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.45 4.30 SQ 4.25 EXPOSED PAD 21 0.45 0.40 0.35 PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 111.
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ADE7880 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10193-0-3/12(A) Rev.