Datasheet

ADE7854/ADE7858/ADE7868/ADE7878 Data Sheet
Rev. G | Page 60 of 100
The line cycle apparent energy accumulation mode is activated
by setting Bit 2 (LVA) in the LCYCMODE register. The apparent
energy accumulated over an integer number of zero crossings is
written to the x VAH R accumulation registers after the number
of zero crossings specified in LINECYC register is detected. When
using the line cycle accumulation mode, set Bit 6 (RSTREAD) of
the LCYCMODE register to Logic 0 because a read with the reset
of xVAH R registers is not available in this mode.
Phase A, Phase B, and Phase C zero crossings are, respectively,
included when counting the number of half line cycles by setting
Bits[5:3] (ZXSEL[x]) in the LCYCMODE register. Any combi-
nation of the zero crossings from all three phases can be used
for counting the zero crossing. Select only one phase at a time
for inclusion in the zero-crossings count during calibration.
For details on setting the LINECYC register and Bit 5 (LENERGY)
in the MASK0 interrupt mask register associated with the line
cycle accumulation mode, see the Line Cycle Active Energy
Accumulation Mode section.
WAVEFORM SAMPLING MODE
The waveform samples of the current and voltage waveform,
the active, reactive, and apparent power outputs are stored
every 125 µs (8 kHz rate) into 24-bit signed registers that can be
accessed through various serial ports of the ADE7854/ADE7858/
ADE7868/ADE7878. Table 21 provides a list of registers and their
descriptions.
Table 21. Waveform Registers List
Register Description
IAWV Phase A current
VAWV Phase A voltage
IBWV Phase B current
VBWV Phase B voltage
ICWV Phase C current
VCWV
Phase C voltage
INWV
Neutral current, available in the ADE7868
and ADE7878 only
AVA Phase A apparent power
BVA Phase B apparent power
CVA Phase C apparent power
AWAT T Phase A active power
BWAT T Phase B active power
CWAT T Phase C active power
AVAR Phase A reactive power
BVAR Phase B reactive power
CVAR
Phase C reactive power
Bit 17 (DREADY) in the STATUS0 register can be used to
signal when the registers listed in Table 21 can be read using
I
2
C or SPI serial ports. An interrupt attached to the flag can be
enabled by setting Bit 17 (DREADY) in the MASK0 register.
See the Digital Signal Processor section for more details on
Bit DREADY.
The ADE7854/ADE7858/ADE7868/ADE7878 contain a high
speed data capture (HSDC) port that is specially designed to
provide fast access to the waveform sample registers. Read the
HSDC Interface section for more details.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7854/ADE7858/ADE7868/ADE7878
work on 32-, 16-, or 8-bit words. All registers listed in Table 21
are transmitted signed extended from 24 bits to 32 bits (see
Figure 37).
ENERGY-TO-FREQUENCY CONVERSION
The ADE7854/ADE7858/ADE7868/ADE7878 provide three
frequency output pins: CF1, CF2, and CF3. The CF3 pin is
multiplexed with the HSCLK pin of the HSDC interface. When
HSDC is enabled, the CF3 functionality is disabled at the pin.
CF1 and CF2 pins are always available. After initial calibration
at manufacturing, the manufacturer or end customer verifies
the energy meter calibration. One convenient way to verify the
meter calibration is to provide an output frequency propor-
tional to the active, reactive, or apparent powers under steady
load conditions. This output frequency can provide a simple,
single-wire, optically isolated interface to external calibration
equipment. Figure 75 illustrates the energy-to-frequency
conversion in the ADE7854/ADE7858/ADE7868/ADE7878.
The DSP computes the instantaneous values of all phase powers:
total active, fundamental active, total reactive, fundamental
reactive, and apparent. The process in which the energy is sign
accumulated in various xWATTHR, xVARHR, and xVAHR
registers has already been described in the energy calculation
sections: Active Energy Calculation, Reactive Energy Calculation,
and Apparent Energy Calculation. In the energy-to-frequency
conversion process, the instantaneous powers generate signals
at the frequency output pins (CF1, CF2, and CF3). One digital-
to-frequency converter is used for every CFx pin. Every converter
sums certain phase powers and generates a signal proportional
to the sum. Two sets of bits decide what powers are converted.
First, Bits[2:0] (TERMSEL1[2:0]), Bits[5:3] (TERMSEL2[2:0]),
and Bits[8:6] (TERMSEL3[2:0]) of the COMPMODE register
decide which phases, or which combination of phases, are added.
The TERMSEL1 bits refer to the CF1 pin, the TERMSEL2 bits
refer to the CF2 pin, and the TERMSEL3 bits refer to the CF3
pin. The TERMSELx[0] bits manage Phase A. When set to 1,
Phase A power is included in the sum of powers at the CFx
converter. When cleared to 0, Phase A power is not included.
The TERMSELx[1] bits manage Phase B, and the TERMSELx[2]
bits manage Phase C. Setting all TERMSELx bits to 1 means all
3-phase powers are added at the CFx converter. Clearing all
TERMSELx bits to 0 means no phase power is added and no
CF pulse is generated.