Datasheet

Data Sheet ADE7816
Rev. A | Page 7 of 48
HSDC Interface Timing
Table 4. HSDC Interface Timing Parameter
Parameter Symbol Min Max Unit
HSA to HSCLK Edge t
SS
0 ns
HSCLK Period 125 ns
HSCLK Low Pulse Width t
SL
50 ns
HSCLK High Pulse Width t
SH
50 ns
Data Output Valid After HSCLK Edge t
DAV
40 ns
Data Output Fall Time t
DF
20 ns
Data Output Rise Time t
DR
20 ns
HSCLK Rise Time t
SR
10 ns
HSCLK Fall Time t
SF
10 ns
HSD Disable After HSA Rising Edge t
DIS
5 ns
HSA High After HSCLK Edge t
SFS
0 ns
MSB LSBINTERMEDIATE BITS
t
SFS
t
DIS
t
SS
t
SL
t
DF
t
SH
t
DAV
t
SR
t
SF
t
DR
HSD
HSCLK
HSA
10390-004
Figure 4. HSDC Interface Timing
Load Circuit for All Timing Specifications
2mA I
OL
800µA I
OH
1.6V
TO OUTPUT
PIN
C
L
50pF
10390-005
Figure 5. Load Circuit for All Timing Specifications