Datasheet

ADE7816 Data Sheet
Rev. A | Page 40 of 48
Address
Register
Name R/W
1
Bit
Length
Bit Length During
Communication
2
Type
3
Default
Value
4
Description
0xE607 Period R 16 16 U N/A Line period.
0xE608 CHNOLOAD R 16 16 U N/A Channel no load register.
0xE609 to
0xE60B
Reserved For proper operation, do not write to
these addresses.
0xE60C LINECYC R/W 16 16 U 0xFFFF Line cycle accumulation mode count.
0xE60D ZXTOUT R/W 16 16 U 0xFFFF Zero-crossing timeout count.
0xE60E COMPMODE R/W 16 16 U 0x01FF Computation mode register.
0xE60F
Gain
R/W
16
16
U
0x0000
PGA gains at ADC inputs (see Table 22).
0xE610 to
0xE616
Reserved
This register should be ignored.
0xE617 CHSIGN R 16 16 U N/A Power sign register.
0xE618 CONFIG R/W 16 16 U 0x0000 Configuration register.
0xE700 MMODE R/W 8 8 U 0x1C Measurement mode register.
0xE701 ACCMODE R/W 8 8 U 0x00 Accumulation mode register.
0xE702
LCYCMODE
R/W
8
8
U
0x78
Line accumulation mode.
0xE703 PEAKCYC R/W 8 8 U 0x00 Peak detection half line cycles.
0xE704 SAGCYC R/W 8 8 U 0x00 Sag detection half line cycles.
0xE705 Reserved This register should be ignored.
0xE706 HSDC_CFG R/W 8 8 U 0x00 HSDC configuration register.
0xE707
Version
R/W
8
8
U
Version of die.
0xE7E3 Reserved R/W 8 8 U 0x00 Register protection (see the Register
Protection section).
0xE7FE Reserved Register protection key (see the Register
Protection section).
0xEBFF Reserved 8 8 This address can be used in manipulating
the
SS
/HSA pin when SPI is chosen as
the active port (see the Communication
section for details).
0xEC00 Reserved This register should be ignored.
0xEC01 CONFIG2 R/W 8 8 U 0x00 Configuration register (see Table 29).
1
R is read, and W is write.
2
32 ZP is a 24- or 20-bit, signed or unsigned register that is transmitted as a 32-bit word with 8 or 12 MSBs, respectively, padded with 0s. 32 SE is a 24-bit, signed register
that is transmitted as a 32-bit word that is sign extended to 32 bits.
3
U indicates an unsigned register, and S indicates a signed register in twos complement format.
4
N/A is not applicable.
REGISTER DESCRIPTIONS
Table 16. HPFDIS Register (Address 0x4389)
Bits Default Value Description
[23:0] 0x000000 When HPFDIS = 0x000000, all high-pass filters in voltage and current channels are enabled.
When the register is set to any nonzero value, all high-pass filters are disabled.
Table 17. IPEAK Register (Address 0xE500)
Bits Bit Name Default Value Description
[31:27] Reserved 0x00000 These bits should be ignored.
26 IPCHANNEL2 0x0 The C or F current channel generated the IPEAKVAL[23:0] value.
25 IPCHANNEL1 0x0 The B or E current channel generated the IPEAKVAL[23:0] value.
24 IPCHANNEL0 0x0 The A or D current channel generated the IPEAKVAL[23:0] value.
[23:0] IPEAKVAL[23:0] 0x0 Current channel peak value
Table 18. VPEAK Register (Address 0xE501)
Bits Bit Name Default Value Description
[31:24] Reserved 0x00000 These bits should be ignored.
[23:0] VPEAKVAL[23:0] 0x0 Voltage channel peak value.