Datasheet
ADE7816 Data Sheet
Rev. A | Page 32 of 48
I
2
C Read Operation
The read operation, using the I
2
C interface of the ADE7816, is
accomplished in two stages. The first stage sets the pointer to
the address of the register; the second stage reads the contents
of the register (see Figure 40).
The first stage is initiated when the master generates a start con-
dition. It consists of one byte, representing the address of the
ADE7816, followed by the 16-bit address of the target register. The
ADE7816 acknowledges every byte received. The address byte is
similar to the address byte of a write operation and is equal to 0x70
(see the I
2
C Write Operation section for details). After the last
byte of the register address is sent and acknowledged by the
ADE7816, the second stage begins with the master generating
a new start condition, followed by an address byte. The most
significant seven bits of this address byte constitute the address of
the ADE7816, which is 0111000b. Bit 0 of the address byte is a
read/
A
write
E
A
bit. Because this is a read operation, it must be set to 1;
therefore, the first byte of the read operation is 0x71. After this byte
is received, the ADE7816 generates an acknowledge. Then the
ADE7816 sends the value of the register, and, after every eight bits
are received, the master generates an acknowledge. All the bytes
are sent with the most significant bit first. Registers can be 8, 16,
or 32 bits. After the last bit of the register is received, the master
does not acknowledge the transfer but, instead, generates a stop
condition.
SPI-Compatible Interface
The ADE7816 SPI is always a slave of the communication and
consists of four pins (with dual functions): SCLK/SCL, MOSI/SDA,
MISO/HSD, and
A
SS
E
A
/HSA. The functions used in the SPI-compatible
interface are SCLK, MOSI, MISO, and
A
SS
E
A
. The serial clock for
a data transfer is applied at the SCLK logic input. This logic input
has a Schmitt trigger input structure that allows the use of slow
rising (and falling) clock edges. All data transfer operations
synchronize to the serial clock. Data shifts into the ADE7816
at the MOSI logic input on the falling edge of SCLK, and the
ADE7816 samples it on the rising edge of SCLK. Data shifts out
of the ADE7816 at the MISO logic output on a falling edge of
SCLK and can be sampled by the master device on the raising
edge of SCLK. The most significant bit of the word is shifted in
and out first. The maximum serial clock frequency that is
supported by this interface is 2.5 MHz. MISO stays in high
impedance when no data is transmitted from the ADE7816.
Figure 38 shows details of the connection between the ADE7816
SPI and a master device containing a SPI interface.
MOSI/SDA
MISO/HSD
SCLK/SCL
ADE7816
MOSI
MISO
SCK
SPI DEVICE
SS/HSA SS
10390-024
Figure 38. Connecting the ADE7816 SPI with a SPI Device
ACKNOWLEDGE
GENERATED BY
ADE7816
START
STOP
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S0
15
SLAVE ADDRESS
MS 8 BITS OF
REGISTER ADDRESS
LS 8 BITS OF
REGISTER ADDRESS
BYTE 3 (MS)
OF REGISTER
BYTE 2 OF REGISTER BYTE 1 OF REGISTER
BYTE 0 (LS) OF
REGISTER
87 031 1615 87 0 07
1110000
10390-022
Figure 39. I
2
C Write Operation of a 32-Bit Register
ACKNOWLEDGE
GENERATED BY
ADE7816
ACKNOWLEDGE
GENERATED BY
MASTER
START
S
A
C
K
A
C
K
A
C
K
0
15
SLAVE ADDRESS
MSB 8 BITS OF
REGISTER ADDRESS
LSB 8 BITS OF
REGISTER ADDRESS
87 0
1110000
START
STOP
S
A
C
K
A
C
K
A
C
K
A
C
K
S0
SLAVE ADDRESS
BYTE 3 (MSB)
OF REGISTER
BYTE 2 OF
REGISTER
BYTE 1 OF
REGISTER
BYTE 0 (LSB)
OF REGISTER
31 16 15 8
7
0
07
1110001
ACKNOWLEDGE
GENERATED BY
ADE7816
N
O
A
C
K
10390-023
Figure 40. I
2
C Read Operation of a 32-Bit Register