Datasheet

ADE7816 Data Sheet

Rev. A | Page 10 of 48

Pin No. Mnemonic Description

this data sheet as Current Channel D. Connect this input in a single-ended configuration with a maximum

signal level of ±0.5 V with respect to IN.

24 AVDD On-Chip 2.5 V Analog Low Dropout (LDO) Regulator Access. Do not connect external active circuitry to this

pin. Decouple this pin with a 4.7 µF capacitor in parallel with a ceramic 220 nF capacitor.

25 AGND Ground Reference. This pin provides the ground reference for the analog circuitry. Tie this pin to the analog

ground plane or to the quietest ground reference in the system. Use this quiet ground reference for all

analog circuitry, such as antialiasing filters and current and voltage transducers.

26 VDD Supply Voltage. This pin provides the supply voltage and should be set at 3.3 V ± 10% for specified operation.

Decouple this pin to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.

27 CLKIN Master Clock. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT-cut

crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7816. The clock

frequency for specified operation is 16.384 MHz. Use ceramic load capacitors of a few tens of picofarads (pF)

with the gate oscillator circuit. Refer to the crystal manufacturer data sheet for load capacitance requirements.

28 CLKOUT A crystal can be connected across this pin and CLKIN (as stated in the description for Pin 27) to provide

a clock source for the ADE7816. The CLKOUT pin can drive one CMOS load when either an external clock

is supplied at CLKIN or a crystal is being used.

29, 32

IRQ0

IRQ1

Interrupt Request Outputs. These are active low logic outputs. See the Interrupts section for a detailed

presentation of the events that can trigger interrupts.

35 HSCLK Serial Clock Output for the HSDC Port.

36 SCLK/SCL Serial Clock Input for the SPI Port/Serial Clock Input for the I

C Port. All serial data transfers are synchronized to

this clock (see the Communication section). This pin has a Schmidt trigger input for use with a clock source

that has a slow edge transition time (for example, opto-isolator outputs).

37 MISO/HSD Data Output for SPI Port/Data Output for HSDC Port.

38 MOSI/SDA Data Input for SPI Port/Data Output for I

C Port.

/HSA Slave Select for SPI Port/HSDC Port Active.

EP Exposed

Pad

Exposed Pad. Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on

the PCB to confer mechanical strength to the package. Connect the pads to AGND and DGND.