Six Current Channels, One Voltage Channel Energy Metering IC ADE7816 Data Sheet FEATURES voltage and current. The device incorporates seven sigma-delta (Σ-Δ) ADCs with a high accuracy energy measurement core. The six current input channels allow multiple loads to be measured simultaneously. The voltage channel and the six current channels each have a complete signal path allowing for a full range of measurements.
ADE7816 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Energy Gain Calibration ........................................................... 24 General Description ......................................................................... 1 Energy Offset Calibration ......................................................... 24 Functional Block Diagram ..............................................................
Data Sheet ADE7816 SPECIFICATIONS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter 1, 2 ACCURACY Active Energy Measurement Active Energy Measurement Error (per Channel) Min Typ Unit Test Conditions/Comments 0.1 % 0.2 % 0.
ADE7816 Parameter 1, 2 WAVEFORM SAMPLING Current and Voltage Channels Signal-to-Noise Ratio, SNR Signal-to-Noise-and-Distortion Ratio, SINAD Bandwidth (−3 dB) TIME INTERVAL BETWEEN CHANNELS Measurement Error REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Output Impedance Temperature Coefficient Data Sheet Min Typ Max Unit 70 60 2 dB dB kHz 0.3 Degrees Line frequency = 45 Hz to 65 Hz, HPF on 1.3 10 V pF Minimum = 1.2 V − 8%; maximum = 1.
Data Sheet ADE7816 TIMING CHARACTERISTICS VDD = 3.3 V ± 10%, AGND = DGND = 0 V, on-chip reference, CLKIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Note that, within the timing tables and diagrams, the dual function pin names are referenced by the relevant function only; see the Pin Configuration and Function Descriptions section for full pin mnemonics and function descriptions. I2C-Compatible Interface Timing Table 2.
ADE7816 Data Sheet SPI Interface Timing Table 3.
Data Sheet ADE7816 HSDC Interface Timing Table 4.
ADE7816 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Regarding the temperature profile used in soldering RoHScompliant parts, Analog Devices, Inc., advises that reflow profiles should conform to J-STD-20 from JEDEC. Refer to the JEDEC website for the latest revision. Table 5.
Data Sheet ADE7816 40 39 38 37 36 35 34 33 32 31 NC SS/HSA MOSI/SDA MISO/HSD SCLK/SCL HSCLK NC NC IRQ1 NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 ADE7816 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 NC IRQ0 CLKOUT CLKIN VDD AGND AVDD IDP IEP NC NOTES 1. NC = NO CONNECT. THESE PINS ARE NOT CONNECTED INTERNALLY AND SHOULD BE LEFT FLOATING. 2. CREATE A SIMILAR PAD ON THE PCB UNDER THE EXPOSED PAD.
ADE7816 Data Sheet Pin No. Mnemonic 24 AVDD 25 AGND 26 VDD 27 CLKIN 28 CLKOUT 29, 32 IRQ0, IRQ1 35 36 HSCLK SCLK/SCL 37 38 39 EP MISO/HSD MOSI/SDA SS/HSA Exposed Pad Description this data sheet as Current Channel D. Connect this input in a single-ended configuration with a maximum signal level of ±0.5 V with respect to IN. On-Chip 2.5 V Analog Low Dropout (LDO) Regulator Access. Do not connect external active circuitry to this pin. Decouple this pin with a 4.
Data Sheet ADE7816 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 0.3 0.2 0 –0.2 –0.4 0.1 0 –0.1 –0.2 –0.6 –0.3 –0.8 –0.4 0.1 1 10 100 CURRENT CHANNEL (% of Full Scale) –0.5 45 1.0 0.8 1.0 PF = +0.5 PF = +1 PF = –0.5 0.8 ERROR (% of Reading) 0.2 0 –0.2 –0.4 0 –0.2 –0.4 –0.8 –0.8 1 10 100 –1.0 0.01 10390-102 0.1 CURRENT CHANNEL (% of Full Scale) 1.0 1.0 VDD = 2.97V 0.8 VDD = 3.30V VDD = 3.63V 1 10 100 PF = +0.87 PF = 0 PF = –0.87 ERROR (% of Reading) 0.6 0.4 0.2 0 –0.2 –0.
ADE7816 0.8 0.4 0.2 0 –0.2 –0.4 0 –0.2 –0.4 –0.6 –0.8 –0.8 0.1 1 10 100 CURRENT CHANNEL (% of Full Scale) –1.0 0.1 0.5 0.4 1.0 PF = +0.87 PF = 0 PF = –0.87 0.8 100 +85°C +25°C –40°C ERROR (% of Reading) 0.6 0.2 0.1 0 –0.1 –0.2 0.4 0.2 0 –0.2 –0.4 –0.3 –0.6 –0.4 –0.8 55 60 65 –1.0 0.1 10390-108 50 FREQUENCY (Hz) Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 1, Temperature = 25°C) over Frequency and Power Factor with Internal Reference 0.8 0.6 0.
Data Sheet 0.8 1.0 +85°C +25°C –40°C 0.8 ERROR (% of Reading) 0.6 0.4 0.2 0 –0.2 –0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –0.8 –1.0 0.1 1 10 100 CURRENT CHANNEL (% of Full Scale) Figure 19. Reactive Energy Error as a Percentage of Reading (Gain = 16, Power Factor = 0) over Temperature with Internal Reference, Integrator On 1.0 0.8 PF = +0.87 PF = 0 PF = –0.87 0.6 ERROR (% of Reading) 0.4 –0.6 10390-113 ERROR (% of Reading) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –1.0 0.
ADE7816 Data Sheet TEST CIRCUIT 3.3V + 0.22µF 24 26 5 VDD DVDD 3.3V 4.7µF AVDD 4.7µF 2 PULL_HIGH 4 0.22µF SS/HSA 39 3 PULL_LOW MOSI/SDA 38 RESET MISO/HSD 37 7 IAP SCLK/SCL 36 8 IAN HSCLK 35 9 IBP 12 IBN IRQ1 32 ADE7816 IRQ0 29 REFIN/OUT 17 13 ICP 20pF CLKOUT 28 14 ICN 4.7µF + 0.1µF 16.384MHz CLKIN 27 20pF 19 IFP NC 1 NC 10 22 IEP NC 11 NC 20 23 IDP NC 21 18 IN NC 30 NC 31 15 VP NC 33 6 25 NC 34 NC 40 10390-007 16 VN AGND 1µF DGND 10kΩ + Figure 22.
Data Sheet ADE7816 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7816 is defined by the following equation: Measurement Error = Energy Registered by ADE7816 − True Energy × 100% True Energy Phase Error Between Channels The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current channels and the voltage channel.
ADE7816 Data Sheet QUICK START After power is supplied to the ADE7816 and communication is established, a set of registers must be written (see Figure 23). Table 8 lists details about each register. This section outlines the procedure for powering up and initializing the ADE7816. Figure 23 shows a flow diagram of the initialization steps. For detailed information, refer to the section of the data sheet that pertains to each step, as indicated in Figure 23.
Data Sheet ADE7816 INPUTS The following section provides details on the ADE7816 input connections that are required for correct functionality. POWER AND GROUND VDD and AGND, DGND To power the ADE7816, a 3.3 V dc input voltage should be provided between the VDD pin and the AGND and DGND pins. In addition, the PULL_HIGH and PULL_LOW pins must be connected to 3.3 V and AGND, respectively. This configuration is shown in Figure 24. 3.
ADE7816 Data Sheet CLKIN AND CLKOUT PGA Gain An external clock or parallel resonant crystal is required to clock the ADE7816. If an external clock source is being used, it should be connected to the CLKIN pin. The required clock frequency for specified operation is 16.384 MHz. Alternatively, a parallel resonant AT-cut crystal can be connected across the CLKIN and CLKOUT pins.
Data Sheet ADE7816 Each analog input pin requires that a simple RC filter be connected to the input. The role of the RC filter is to prevent aliasing. The aliasing effect is caused by frequency components (which are higher than half the sampling rate of the ADC) folding back and appearing in the sampled signal at a frequency that is below half the sampling rate. Aliasing is an artifact of all sampled systems.
ADE7816 Data Sheet ENERGY MEASUREMENTS This section describes the energy measurements available in the ADE7816. For information about the theory behind these measurements, refer to the AN-1137 Application Note. STARTING AND STOPPING THE DSP To obtain energy measurements, the internal processor must first be started by setting the run register (Address 0xE228) to 0x0001.
Data Sheet ADE7816 The content of the active energy register overflows from full-scale positive (0x7FFFFFFF) to full-scale negative (0x80000000) and continues to increase in value when the active power is positive. Conversely, if the active power is negative, the energy register underflows from full-scale negative (0x80000000) to full-scale positive (0x7FFFFFFF) and continues decreasing in value.
ADE7816 Data Sheet time should be written to the LINECYC register (Address 0xE60C) as an integer number of half line cycles. The ADE7816 can accumulate energy for up to 65,535 half line cycles. This equates to an accumulation period of approximately 655 sec with 50 Hz inputs, and 546 sec with 60 Hz inputs. The reactive energy register content overflows from full-scale positive (0x7FFFFFFF) to full-scale negative (0x80000000) and continues to increase in value when the reactive power is positive.
Data Sheet ADE7816 VARNOLOAD (Address 0x43B0) registers. When in the no load condition, the active and reactive energies are no longer accumulated in the energy registers. Note that each of the six channels has a separate no load circuit. ROOT MEAN SQUARE MEASUREMENT Root mean square (rms) is a measurement of the magnitude of an ac signal. Specifically, the rms of an ac signal is equal to the amount of dc required to produce an equivalent amount of power in the load.
ADE7816 Data Sheet ENERGY CALIBRATION CHANNEL MATCHING The ADE7816 provides individual channel gain registers that allow the six current channels and the voltage channel to be matched. Matching the channels simplifies the calibration process.
Data Sheet ADE7816 ENERGY PHASE CALIBRATION The ADE7816 is designed to function with a variety of current transducers, including those that induce inherent phase errors. A phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected to achieve accurate power readings. The errors associated with phase mismatch are particularly noticeable at low power factors.
ADE7816 Data Sheet POWER QUALITY FEATURES also be configured to trigger an interrupt on the external pin by setting the DREADY bit (Bit 17) in the MASK0 register (Address 0xE50A). With the specified full-scale analog input signal of 0.5 V, the expected reading on the current and voltage waveform register is approximately ±5,989,256 (dec). This section describes the power quality features that are available in the ADE7816.
Data Sheet ADE7816 Zero-Crossing Timeout Each zero-crossing detection circuit has an associated timeout register. This register is loaded with the value that is written into the 16-bit ZXTOUT register (Address 0xE60D) and is decremented by 1 LSB every 62.5 μs (16 kHz clock). The register is reset to the ZXTOUT value every time a zero crossing is detected. The default value of this register is 0xFFFF.
ADE7816 Data Sheet Setting the OVLVL and OILVL Registers The content of the overvoltage (OVLVL) and overcurrent (OILVL), 24-bit, unsigned registers is compared to the absolute value of the voltage and current channels. The maximum value of these registers is 5,928,256 (0x5A7540) with full scale inputs. When either the OVLVL or OILVL register is equal to this value, the overvoltage or overcurrent conditions are never detected.
Data Sheet ADE7816 This method of determining the power factor does not take into account the effect of any harmonics. When Bits[10:9] (ANGLESEL) of the COMPMODE register are set to 10b, the time delays (angles) between current channels are measured. Table 10 shows the current channel-to-channel delay measure-ments that are available. Table 10.
ADE7816 Data Sheet gi, where i = 0, 1, 2, …, 31 is the coefficient of the generating polynomial defined by the IEEE802.3 standard as follows: CHECKSUM The ADE7816 has a 32-bit checksum register (Address 0xE51F) that ensures that certain important configuration registers maintain their desired value during normal operation.
Data Sheet ADE7816 OUTPUTS This section describes the outputs from the ADE7816. E A INTERRUPTS The ADE7816 has two interrupt pins, IRQ0 and IRQ1. Each pin is managed by a 32-bit interrupt mask register, MASK0 and MASK1 (Address 0xE50A and Address 0xE50B), respectively. To enable an interrupt, a bit in the MASKx register must be set to 1. To disable an interrupt, the bit must be cleared to 0.
ADE7816 Data Sheet I2C Read Operation SPI-Compatible Interface The read operation, using the I2C interface of the ADE7816, is accomplished in two stages. The first stage sets the pointer to the address of the register; the second stage reads the contents of the register (see Figure 40). The ADE7816 SPI is always a slave of the communication and consists of four pins (with dual functions): SCLK/SCL, MOSI/SDA, MISO/HSD, and SS/HSA.
Data Sheet ADE7816 it begins to transmit its contents on the MISO line when the next SCLK high-to-low transition occurs; thus, the master can sample the data on a low-to-high SCLK transition. After the master receives the last bit, it sets the SS and SCLK lines high, and the communication ends. The data lines, MOSI and MISO, go into a high impedance state (see Figure 41). The SS logic input is the chip select input. This input is used when multiple devices share the serial bus.
ADE7816 Data Sheet HSDC Interface The high speed data capture (HSDC) interface is disabled by default. It can be used only if the ADE7816 is configured with an I2C interface. The ADE7816 SPI interface cannot be used simultaneously with the HSDC port. Bit 6 (HSDCEN) in the CONFIG register (Address 0xE618) activates HSDC when set to 1. If the HSDCEN bit is cleared to 0, the default value, the HSDC interface is disabled. Setting the HSDCEN bit to 1 when the SPI is in use does not have any effect.
Data Sheet ADE7816 Table 11 lists the time that is required to execute an HSDC data transfer for all HSDC_CFG register settings. Table 11. Communication Times for Various HSDC Settings HXFER[1:0] 01 01 01 01 01 01 HCLK 0 1 0 1 0 1 Communication Time (μs) 28 56 33.25 66.5 51.625 103.25 N/A means not applicable. HSCLK 31 HSD 0 31 0 31 IAWV/IDWV (32) VWV (32) 0 31 IBWV/IEWV (32) 0 0000000 (32) 10390-028 HSA Figure 44.
ADE7816 Data Sheet REGISTERS REGISTER PROTECTION REGISTER FORMAT To protect the integrity of the data stored in the data memory (located at Address 0x4380 to Address 0x43BE), a write protection mechanism is available. By default, the protection is disabled, and registers that are located between Address 0x4380 and Address 0x43BE can be written without restriction. When the protection is enabled, no writes to these registers are allowed.
Data Sheet ADE7816 REGISTER MAPS Table 12.
ADE7816 Data Sheet Address 0x43AD Register Name VARTHR1 R/W 1 R/W Bit Length 24 Bit Length During Communication 2 32 ZP Type 3 U Default Value 0x000000 0x43AE VARTHR0 R/W 24 32 ZP U 0x000000 0x43AF 0x43B0 APNOLOAD VARNOLOAD RW R/W 24 24 32 ZP 32 ZPSE U S 0x000000 0x000000 0x43B1 PCF_A_COEFF R/W 24 32 ZPSE U 0x000000 0x43B2 PCF_B_COEFF R/W 24 32 ZPSE U 0x000000 0x43B3 PCF_C_COEFF R/W 24 32 ZPSE U 0x000000 0x43B4 PCF_D_COEFF R/W 24 32 ZPSE U 0x000000 0x43B5
Data Sheet ADE7816 Table 14.
ADE7816 Address 0xE607 0xE608 0xE609 to 0xE60B 0xE60C 0xE60D 0xE60E 0xE60F 0xE610 to 0xE616 0xE617 0xE618 0xE700 0xE701 0xE702 0xE703 0xE704 0xE705 0xE706 0xE707 0xE7E3 Data Sheet Register Name Period CHNOLOAD Reserved R/W 1 R R Bit Length 16 16 Bit Length During Communication 2 16 16 Type 3 U U Default Value 4 N/A N/A LINECYC ZXTOUT COMPMODE Gain Reserved R/W R/W R/W R/W 16 16 16 16 16 16 16 16 U U U U 0xFFFF 0xFFFF 0x01FF 0x0000 CHSIGN CONFIG MMODE ACCMODE LCYCMODE PEAKCYC SAGCYC Reserved HSD
Data Sheet ADE7816 Note that Address 0xE502, Address 0xE503, Address 0xE50A, and Address 0xE50B are listed in Table 30 and Table 31. Table 19. CHSTATUS Register (Address 0xE600) Bits [15:6] 5 4 3 [2:0] Bit Name Reserved OICHANNEL2 OICHANNEL1 OICHANNEL0 Reserved Default Value 0x000 0x0 0x0 0x0 0x000 Description These bits should be ignored. The C or F current channel generated the overcurrent event. The B or E current channel generated the overcurrent event.
ADE7816 Data Sheet Bits [5:3] Bit Name PGA2[2:0] Default Value 0x000 [2:0] PGA1[2:0] 0x000 Description Voltage channel gain selection. 000: gain = 1 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 101, 110, 111: reserved. Gain selection for the A, B, and C current channels. 000: gain = 1. 001: gain = 2. 010: gain = 4. 011: gain = 8. 100: gain = 16. 101, 110, 111: reserved. Table 23.
Data Sheet ADE7816 Table 26. ACCMODE Register (Address 0xE701) Bits 7 Bit Name REVRPSEL Default Value 0x0 6 REVAPSEL 0x0 [5:4] [3:2] Reserved VARACC[1:0] 0x00 0x00 [1:0] WATTACC[1:0] 0x00 Description 0: the sign of the reactive power is monitored on the A, B, and C channels. 1: the sign of the reactive power is monitored on the D, E, and F channels. Bit 14 (CHANNEL_SEL) of COMPMODE must be set to the same current channels.
ADE7816 Data Sheet Interrupt Enable and Interrupt Status Registers Table 30. STATUS0 Register (Address 0xE502) and MASK0 Register (Address 0xE50A) Bits [31:18] 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name Reserved DREADY Reserved Reserved Reserved Reserved REVRP3 REVRP2 REVRP1 Reserved REVAP3 REVAP2 REVAP1 LENERGY Reserved REHF2 REHF1 AEHF2 AEHF1 Default Value 0 0000 0000 0000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Description These bits should be ignored.
Data Sheet ADE7816 OUTLINE DIMENSIONS 0.30 0.23 0.18 31 40 30 0.50 BSC 1 0.80 0.75 0.70 0.45 0.40 0.35 PKG-003438 10 11 20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 4.45 4.30 SQ 4.25 EXPOSED PAD 21 TOP VIEW PIN 1 INDICATOR BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WJJD. 05-06-2011-A PIN 1 INDICATOR 6.10 6.00 SQ 5.90 Figure 48.
ADE7816 Data Sheet NOTES Rev.
Data Sheet ADE7816 NOTES Rev.
ADE7816 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10390-0-12/13(A) Rev.
