Datasheet

Data Sheet ADE7763
Rev. C | Page 45 of 56
SUSPENDING FUNCTIONALITY
The analog and the digital circuit can be suspended separately.
The analog portion can be suspended by setting the ASUSPEND
bit (Bit 4) of the mode register to logic high—see the Mode
Register (0x09) section. In suspend mode, all waveform samples
from the ADCs are set to 0s. The digital circuitry can be halted
by stopping the CLKIN input and maintaining a logic high or
low on the CLKIN pin. The ADE7763 can be reactivated by
restoring the CLKIN input and setting the ASUSPEND bit to
logic low.
CHECKSUM REGISTER
The ADE7763 has a checksum register (CHECKSUM[5:0]) to
ensure that the data bits received in the last serial read operation
are not corrupted. The 6-bit checksum register is reset before
the first bit (MSB of the register to be read) is put on the DOUT
pin. During a serial read operation, when each data bit becomes
available upon the rising edge of SCLK, the bit is added to the
checksum register. At the end of the serial read operation, the
content of the checksum register is equal to the sum of all ones
previously read in the register. Using the checksum register, the
user can determine if an error has occurred during the last read
operation. Note that a read to the checksum register also
generates a checksum of the checksum register itself.
CONTENT OF REGISTER (n-bytes)
CHECKSUM REGISTER ADDR: 0x3E
+
+
DOUT
04481-A-070
Figure 79. Checksum Register for Serial Interface Read
SERIAL INTERFACE
All ADE7763 functionality is accessible via several on-chip
registers—see Figure 80. The contents of these registers can be
updated or read using the on-chip serial interface. After power-
on or toggling the
RESET
pin low and a falling edge on
CS
, the
ADE7763 is placed in communication mode. In communica-
tion mode, the ADE7763 expects a write to its communication
register. The data written to the communication register
determines whether the next data transfer operation is a read or
a write and which register is accessed. Therefore, all data
transfer operations with the ADE7763, whether a read or a
write, must begin with a write to the communication register.
COMMUNICATION
REGISTER
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER n–1
REGISTER n
REGISTER
ADDRESS
DECODE
DIN
DOUT
04481-A-071
Figure 80. Addressing ADE7763 Registers via the Communication Register
The communication register is an 8-bit-wide register. The MSB
determines whether the next data transfer operation is a read or
a write. The 6 LSBs contain the address of the register to be
accessed—see the Communication Register section for a more
detailed description.
Figure 81 and Figure 82 show the data transfer sequences for a
read and write operation, respectively. A data transfer is complete
when the LSB of the ADE7763 register being addressed (for a
write or a read) is transferred to or from the ADE7763. When
multiple reads or writes occur in succession, a time delay of
2600 ns must be included between the last falling SCLK edge on
the first read or write to the first SCLK falling edge of the next
read or write. , During that delay time, the
CS
pin must be high for
at least 100 ns.
MULTIBYTE
COMMUNICATION REGISTER WRITE
DIN
SCLK
CS
DOU
T
READ DATA
ADDRESS00
04481-A-072
Figure 81. Reading Data from the ADE7763 via the Serial Interface
COMMUNICATION REGISTER WRITE
DIN
SCLK
CS
ADDRESS01
04481-A-073
MULTIBYTE READ DATA
Figure 82. Writing Data to the ADE7763 via the Serial Interface