Single-Phase Active and Apparent Energy Metering IC ADE7763 Data Sheet FEATURES perform active and apparent energy measurements, line-voltage period measurements, and rms calculation on the voltage and current channels.
ADE7763 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Active Power Calculation .......................................................... 25 General Description ......................................................................... 1 Energy Calculation ..................................................................... 27 Functional Block Diagram ..............................................................
Data Sheet ADE7763 REVISION HISTORY 1/13—Rev. B to Rev. C Changes to Figure 1........................................................................... 1 Moved Revision History Section ..................................................... 3 Changes to Table 2 ............................................................................ 6 Changes to Table 4 ............................................................................ 9 Changes to Figure 24 ...................................................
ADE7763 Data Sheet SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = –40°C to +85°C. Table 1. Specifications 1, 2 Parameter ENERGY MEASUREMENT ACCURACY Active Power Measurement Error Channel 1 Range = 0.5 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel 1 Range = 0.25 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel 1 Range = 0.
Data Sheet Parameter REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Current Source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS RESET, DIN, SCLK, CLKIN, and CS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS SAG and IRQ Output High Voltage, VOH Output Low Voltage, VOL ZX and DOUT Output High Voltage, VOH Output Low Voltage, VOL CF Output High Voltage, VOH Output Lo
ADE7763 Data Sheet TIMING CHARACTERISTICS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 2. Timing Characteristics1, 2 Parameter Write Timing t1 t2 t3 t4 t5 t6 t7 t8 Spec Unit Test Conditions/Comments 50 50 50 10 5 4 3200 100 ns min ns min ns min ns min ns min μs min ns min ns min) CS falling edge to first SCLK falling edge. SCLK logic high pulse width. SCLK logic low pulse width.
Data Sheet ADE7763 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3.
ADE7763 Data Sheet TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7763 is defined by the following formula: Percent Error = Energy Register ADE7763 − True Energy × 100% True Energy Phase Error between Channels The digital integrator and the high-pass filter (HPF) in Channel 1 have a nonideal phase response.
Data Sheet ADE7763 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET 1 20 DIN DVDD 2 19 DOUT AVDD 3 18 SCLK V1P 4 17 CS V1N 5 ADE7763 V2P 7 14 IRQ AGND 8 13 SAG REFIN/OUT 9 12 ZX DGND 10 11 CF 04481-A-005 16 CLKOUT TOP VIEW V2N 6 (Not to Scale) 15 CLKIN Figure 5. Pin Configuration (SSOP Package) Table 4. Pin Function Descriptions Pin No.
ADE7763 Data Sheet Pin No. 14 Mnemonic IRQ 15 CLKIN 16 CLKOUT 17 CS 18 SCLK 19 DOUT 20 DIN 1 Description Interrupt Request Output. This is an active low, open-drain logic output. Maskable interrupts include active energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the Interrupts section. Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.
Data Sheet ADE7763 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.4 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE 0.3 0.2 0.6 +25°C, PF = 1 0.1 0 –40°C, PF = 0.5 –0.1 –0.2 +25°C, PF = 0.5 –0.3 100 –1.0 0.1 100 1.0 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE 0.8 0.6 0.4 0 +25°C, PF = 1 –0.2 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE 0.4 +85°C, PF = 1 0.2 ERROR (%) –0.4 0.2 –40°C, PF = 1 +25°C, PF = 1 0 –0.2 –0.4 –0.6 +25°C, PF = 0.5 +85°C, PF = 0.5 –40°C, PF = 0.5 –0.6 –0.
ADE7763 Data Sheet 1.2 1.0 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE 1.0 0.8 0.6 0.8 0.4 PF = 0.5 ERROR (%) 0.4 0.2 PF = 1 0 +25°C, PF = 0.5 +25°C, PF = 1 –0.2 –40°C, PF = 0.5 –0.6 –0.4 47 49 51 53 55 57 59 61 63 65 –1.0 0.1 04481-A-012 45 1 10 100 FULL-SCALE CURRENT (%) Figure 12. Active Energy Error as a Percentage of Reading (Gain = 8) over Frequency with Internal Reference and Integrator Off 04481-A-016 –0.8 FREQUENCY (Hz) Figure 15.
Data Sheet ADE7763 0.5 16 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE 0.4 0.3 14 5.25V 12 10 0.1 5.00V 0 HITS ERROR (%) 0.2 8 –0.1 6 –0.2 4.75V 4 –0.3 1 10 0 –15 04481-A-081 –0.5 0.1 100 FULL-SCALE CURRENT (%) –10 –5 0 5 10 15 04481-A-021 2 –0.4 20 CH1 OFFSET (0p5V_1X) (mV) Figure 18. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator On Figure 20. Channel 1 Offset (Gain = 1) 0.
ADE7763 Data Sheet THEORY OF OPERATION ANALOG INPUTS Table 5. Maximum Input Signal Levels for Channel 1 The ADE7763 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N is ±0.5 V. In addition, the maximum signal level on analog inputs for V1P/V1N and V2P/V2N is ±0.5 V with respect to AGND. Max Signal Channel 1 0.5 V 0.25 V 0.125 V 0.0625 V 0.0313 V 0.0156 V 0.
Data Sheet ADE7763 The current and voltage rms offsets can be adjusted with the IRMSOS and VRMSOS registers—see the Channel 1 RMS Offset Compensation and Channel 2 RMS Offset Compensation sections. DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION VOS IOS VI 2 di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR IOS V A di/dt sensor detects changes in magnetic field caused by ac current. Figure 27 shows the principle of a di/dt current sensor.
PHASE (Degrees) ADE7763 Data Sheet –88.0 frequency noise, necessitating a more effective antialiasing filter to avoid noise due to aliasing—see the Antialias Filter section. –88.5 When the digital integrator is switched off, the ADE7763 can be used directly with a conventional current sensor such as a current transformer (CT) or with a low resistance current shunt. –89.0 ZERO-CROSSING DETECTION –89.5 –90.0 102 04481-A-030 –90.5 103 FREQUENCY (Hz) Figure 29.
Data Sheet ADE7763 every 128/CLKIN seconds. The register is reset to its userprogrammed, full-scale value when a zero crossing on Channel 2 is detected. The default power-on value in this register is 0xFFF. If the internal register decrements to 0 before a zero crossing is detected and the DISSAG bit in the mode register is Logic 0, the SAG pin goes active low. The absence of a zero crossing is also indicated on the IRQ pin if the ZXTO enable bit in the interrupt enable register is set to Logic 1.
ADE7763 Data Sheet LINE VOLTAGE SAG DETECTION PEAK DETECTION In addition to detecting the loss of the line voltage when there are no zero crossings on the voltage channel, the ADE7763 can also be programmed to detect when the absolute value of the line voltage drops below a peak value for a specified number of line cycles. This condition is illustrated in Figure 35. The ADE7763 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value.
Data Sheet ADE7763 Using Interrupts with an MCU input. Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read operation. Figure 38 shows a timing diagram with a suggested implementation of ADE7763 interrupt management using an MCU. At time t1, the IRQ line goes active low, indicating that one or more interrupt events have occurred. Tie the IRQ logic output to a negative edge-triggered external interrupt on the MCU.
ADE7763 Data Sheet Interrupt Timing Review the Serial Interface section before reading this section. As previously described, when the IRQ output goes low, the MCU ISR will read the interrupt status register to determine the source of the interrupt. When reading the status register contents, the IRQ output is set high upon the last falling edge of SCLK of the first byte transfer (read interrupt status register command).
Data Sheet ADE7763 Antialias Filter Reference Circuit Figure 39 also shows an analog low-pass filter (RC) on the input to the modulator. This filter prevents aliasing, which is an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC that are higher than half the sampling rate of the ADC appear in the sampled signal at a frequency below half the sampling rate. Figure 41 illustrates the effect.
ADE7763 Data Sheet 2.42V, 1.21V, 0.6V ×1, ×2, ×4, REFERENCE ×8, ×16 {GAIN[2:0]} V1P {GAIN[4:3]} HPF DIGITAL INTEGRATOR* ADC 1 PGA1 V1 CURRENT RMS (IRMS) CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION dt V1N 50Hz CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (50Hz) 0x1E F73C V1 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV, 15.
Data Sheet ADE7763 CURRENT SIGNAL (i(t)) 0x28 51EC IRMSOS[11:0] IRMS(t) 0x00 LPF3 HPF1 + 24 24 IRMS 04481-A-046 0xD7 AE14 CHANNEL 1 217 216 215 0x1C 82B3 0x00 sgn 225 226 227 Figure 45. Channel 1 RMS Signal Processing IRMS = IRMS0 2 + IRMSOS × 32768 To measure the offset of the rms measurement, two data points are needed from nonzero input values, for example, the base current, Ib, and Imax/100. The offset can be calculated from these measurements.
ADE7763 Data Sheet 2.42V ×1, ×2, ×4, REFERENCE ×8, ×16 {GAIN[7:5]} V2P PGA2 V2 ACTIVE AND REACTIVE ENERGY CALCULATION ADC 2 LPF1 V2N ANALOG V1 INPUT RANGE 0.5V, 0.25V, 0.125V, 62.5mV, 31.25mV 0V 0x2852 0x2581 VRMS CALCULATION AND WAVEFORM SAMPLING (PEAK/SAG/ZX) LPF OUTPUT WORD RANGE 04481-A-048 0x0000 0xDAE8 0xD7AE Figure 47.
Data Sheet ADE7763 The phase calibration register (PHCAL[5:0]) is a twos complement, signed, single-byte register that has values ranging from 0x21 (–31d) to 0x1F (+31d). 0.7 0.6 0.5 0.4 0.3 0.2 0.1 104 FREQUENCY (Hz) Figure 50. Combined Phase Response of HPF and Phase Compensation (10 Hz to 1 kHz) 0.20 0.18 PHASE (Degrees) 0.14 0.12 0.10 0.08 0.06 0.04 0 40 45 50 55 60 65 70 FREQUENCY (Hz) 04481-A-052 0.02 Figure 51.
ADE7763 Data Sheet v(t ) 2 V sin(ω t ) i(t ) 2 I sin(ω t ) (7) (8) 0x19 999A INSTANTANEOUS POWER SIGNAL p(t) = v i-v i cos(2t) ACTIVE REAL POWER SIGNAL = v i where: V is the rms voltage. I is the rms current. VI 0xC CCCD p (t ) v (t ) i (t ) p(t ) VI VI cos(2t ) (9) 0x0 0000 The average power over an integral number of line cycles (n) is given by the expression in Equation 10. nT p (t ) dt VI 04481-A-054 1 nT VOLTAGE v(t) = 2 v sin(t) (10) 0 Figure 53.
Data Sheet ADE7763 APOS[15:0] CURRENT CHANNEL LPF2 + WDIV[7:0] 23 + AENERGY[23:0] 0 UPPER 24 BITS ARE ACCESSIBLE THROUGH AENERGY[23:0] REGISTER % VOLTAGE CHANNEL WGAIN[11:0] 48 0 4 CLKIN OUTPUT LPF2 T WAVEFORM REGISTER VALUES OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL ACTIVE ENERGY REGISTER 04481-A-056 ACTIVE POWER SIGNAL TIME (nT) Figure 55.
ADE7763 Data Sheet APOS[15:0] sgn 26 25 I MULTIPLIER 1 V VOLTAGE SIGNAL– v(t) LPF2 24 + 2-6 2-7 2-8 0x1 9999 + 32 INSTANTANEOUS POWER SIGNAL – p(t) WGAIN[11:0] FOR WAVEFORM ACCUMULATION 0xC CCCD 0x19 999A 04481-A-058 CURRENT SIGNAL – i(t) FOR WAVEF0RM SAMPLING 24 HPF 0x00 0000 Figure 57. Active Power Signal Processing The ADE7763 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal unreadable 49-bit energy register.
Data Sheet ADE7763 Integration Time under Steady Load A digital-to-frequency converter (DFC) is used to generate the CF pulsed output. The DFC generates a pulse each time 1 LSB in the active energy register is accumulated. An output pulse is generated when (CFDEN + 1)/(CFNUM + 1) number of pulses are generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power.
ADE7763 Data Sheet The active power signal (output of LPF2) can be rewritten as VI p (t ) VI cos( 4 f L t ) 2 2 fL 1 8.9 higher output frequencies. The ripple becomes larger as a percentage of the frequency at larger loads and higher output frequencies. This occurs because the integration or averaging time in the energy-to-frequency conversion process is shorter at higher output frequencies.
Data Sheet ADE7763 LINE CYCLE ENERGY ACCUMULATION MODE In line cycle energy accumulation mode, the energy accumulation of the ADE7763 can be synchronized to the Channel 2 zero crossing so that active energy accumulates over an integral number of half line cycles. The advantage of summing the active energy over an integral number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates ripple in the energy calculation.
ADE7763 Data Sheet The apparent power is the maximum power that can be delivered to a load. Vrms and Irms are the effective voltage and current delivered to the load; the apparent power (AP) is defined as Vrms × Irms. The angle θ between the active power and the apparent power generally represents the phase shift due to nonresistive loads. For single-phase applications, θ represents the angle between the voltage and the current signals—see Figure 63.
Data Sheet ADE7763 APPARENT ENERGY CALCULATION 23 VAENERGY[23:0] 0 The apparent energy is given as the integral of the apparent power. 48 (26) % VADIV APPARENT POWER 48 + 0 + Apparent Energy Lim Apparent Power ( nT ) T (27) T 0 n 0 ACTIVE POWER SIGNAL = P T where: n is the discrete number of time samples. T is the time sample period. The discrete time sample period (T) for the accumulation register is 1.1 μs (4/CLKIN).
ADE7763 Data Sheet Integration Times under Steady Load By using the on-chip zero-crossing detection, the ADE7763 accumulates the apparent power signal in the LVAENERGY register for an integral number of half cycles, as shown in Figure 68. The line apparent energy accumulation mode is always active. As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 µs (4/CLKIN).
Data Sheet ADE7763 ENERGIES SCALING PF = 1 Integrator on at 50 Hz Active Wh Apparent Wh × 0.848 Integrator off at 50 Hz Active Wh Apparent Wh × 0.848 Integrator on at 60 Hz Active Wh Apparent Wh × 0.827 Integrator off at 60 Hz Active Wh Apparent Wh × 0.827 PF = 0.707 PF = 0 Wh × 0.707 Wh × 0.848 0 Wh × 0.848 Wh × 0.707 Wh × 0.848 0 Wh × 0.848 Wh × 0.707 Wh × 0.827 0 Wh × 0.827 Wh × 0.707 Wh × 0.827 0 Wh × 0.
ADE7763 Data Sheet Watt Gain The first step of calibrating the gain is to define the line voltage, the base current, and the maximum current for the meter. A meter constant, such as 3200 imp/kWh or 3.2 imp/Wh, needs to be determined for CF. Note that the line voltage and the maximum current scale to half of their respective analog input ranges in this example. The expected CF in Hz is CFexpected (Hz) = MeterConstant (imp/Wh) × Load(W) 3600 s/h × cos(ϕ) (30) where: ϕ is the angle between I and V.
Data Sheet ADE7763 CFIB(nominal) CFDEN = INT CFIB(expected ) −1 (40) 958 CFDEN = INT − 1 = (490 − 1) = 489 1.9556 This value for CFDEN should be loaded into each meter before calibration. The WGAIN register can then be used to finely calibrate the CF output. The following sections explain how to calibrate a meter based on ADE7763 when using a reference meter or an accurate source. For this example: Meter Constant: MeterConstant(imp/Wh) = 3.
ADE7763 Data Sheet LAENERGYIB(expected) = CALCULATE CFDEN VALUE FOR DESIGN CF Accumulati (s) × on Time IB(expected ) INT CFNUM + 1 × WDIV CFDEN + 1 WRITE CFDEN VALUE TO CFDEN REGISTER ADDR. 0x15 = CFDEN SET ITEST = Ib, VTEST = VNOM, PF = 1 where CFIB(expected) (Hz) is calculated from Equation 30, accumulation time is calculated from Equation 33, and the line period is determined from the period register according to Equation 34.
Data Sheet ADE7763 Figure 73. Calibrating Watt Offset Using a Reference Meter 19186 WGAIN = INT − 1 × 2 12 = 480 17174 For this example: Note that WGAIN is a signed, twos complement register. With WDIV and CFNUM set to 0, LAENERGY can be expressed as LAENERGYIB(expected) = INT (CFIB(expected ) × LINECYCIB / 2 × PERIOD × 8 / CLKIN × (CFDEN + 1)) Using Equation 45, APOS is −522 for this example. The calculated Wh/LSB ratio for the active energy register, using Equation 35 is 6.
ADE7763 Data Sheet Calibrating Watt Offset with an Accurate Source Example Figure 74 is the flowchart for watt offset calibration with an accurate source. SET ITEST = IMIN, VTEST = VNOM, PF = 1 Number of Half Line Cycles used at Minimum Current: LINECYC(IMIN) = 35700 Active Energy Reading at Minimum Current: LAENERGYIMIN(nominal) = 1395 The LAENERGYexpected at IMIN is 1255 using Equation 49. LAENERGYIMIN(expected) = SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR.
Data Sheet ADE7763 Phase Calibration Calibrating Phase Using a Reference Meter Example The PHCAL register is provided to remove small phase errors. The ADE7763 compensates for phase error by inserting a small time delay or advance on the voltage channel input. Phase leads up to 1.84° and phase lags up to 0.72° at 50 Hz can be corrected. The error is determined by measuring the active energy at IB and two power factors, PF = 1 and PF = 0.5 inductive. A power factor of 0.
ADE7763 Data Sheet Calibrating Phase with an Accurate Source Example The error using Equation 52 is 9613 − 19186 With an accurate source, line cycle accumulation is a good method of calibrating phase error. The value of LAENERGY must be obtained at two power factors, PF = 1 and PF = 0.5 inductive. Error = 19186 2 2 = 0.0021 0.0021 Phase Error (°) = −Arcsin = − 0.07° 3 SET ITEST = Ib, VTEST = VNOM, PF = 0.5 Using Equation 55, PHCAL is 11.
Data Sheet ADE7763 VAENERGY = Voltage rms compensation is done after the square root. VRMS = VRMS0 + VRMSOS (60) where: VRMS0 is the rms measurement without offset correction. VRMS is linear from full-scale to full-scale/20. To calibrate the offset, two VRMS measurements are required, for example, at Vnominal and Vnominal/10. Vnominal is set at half of the full-scale analog input range so that the smallest linear VRMS reading is at Vnominal/10.
ADE7763 Data Sheet CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER ADDR. 0x15 = CFDEN SET ITEST = Ib, VTEST = VNOM, PF = 1 SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C SET MODE FOR LINE CYCLE ACCUMULATION ADDR. 0x09 = 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR. 0x0A = 0x04 RESET THE INTERRUPT STATUS READ REGISTER ADDR. = 0x0C INTERRUPT? NO YES RESET THE INTERRUPT STATUS READ REGISTER ADDR. = 0x0C INTERRUPT? NO YES CALCULATE WGAIN.
Data Sheet ADE7763 COMMUNICATION REGISTER DIN The analog and the digital circuit can be suspended separately. The analog portion can be suspended by setting the ASUSPEND bit (Bit 4) of the mode register to logic high—see the Mode Register (0x09) section. In suspend mode, all waveform samples from the ADCs are set to 0s. The digital circuitry can be halted by stopping the CLKIN input and maintaining a logic high or low on the CLKIN pin.
ADE7763 Data Sheet The serial interface of the ADE7763 is made up of four signals: SCLK, DIN, DOUT, and CS. The serial clock for a data transfer is applied at the SCLK logic input. This logic input has a Schmitttrigger input structure that allows slow rising and falling clock edges to be used. All data transfer operations are synchronized to the serial clock. Data is shifted into the ADE7763 at the DIN logic input upon the falling edge of SCLK.
Data Sheet ADE7763 logic output enters a high impedance state upon the falling edge of the last SCLK pulse. The read operation can be aborted by bringing the CS logic input high before the data transfer is complete. The DOUT output enters a high impedance state upon the rising edge of CS. Serial Read Operation During a data read operation from the ADE7763, data is shifted out at the DOUT logic output upon the rising edge of SCLK.
ADE7763 Data Sheet REGISTERS Table 9. Summary of Registers by Address Address 0x01 Name WAVEFORM R/W R No.
Data Sheet ADE7763 Address 0x11 Name APOS R/W R/W No.
ADE7763 Data Sheet Address 0x26 Name TEMP R/W R No. Bits 8 Default 0x0 Type 1 S 0x27 PERIOD R 16 0x0 U 0x28– 0x3C 0x3D 0x3E TMODE CHKSUM R/W R 8 6 – 0x0 U U 0x3F DIEREV R 8 – U 1 Description Temperature Register. This is an 8-bit register that contains the result of the latest temperature conversion—see the Temperature Measurement section. Period of the Channel 2 (Voltage Channel) Input Estimated by ZeroCrossing Processing. The MSB of this register is always zero. Reserved.
Data Sheet ADE7763 REGISTER DESCRIPTIONS All ADE7763 functionality is accessed via on-chip registers. Each register is accessed by first writing to the communication register and then transferring the register data. A full description of the serial interface protocol is given in the Serial Interface section. COMMUNICATION REGISTER The communication register is an 8-bit, write-only register that controls the serial data transfer between the ADE7763 and the host processor.
ADE7763 15 Bit Mnemonic WAVSEL1, 0 POAM Default Value 00 0 Description Use these bits to select the source of the sampled data for the waveform register. WAVSEL1, 0 Length Source 0 0 24 bits, active power signal (output of LPF2) 0 1 Reserved 1 0 24 bits, Channel 1 1 1 24 bits, Channel 2 Writing Logic 1 to this bit allows only positive active power to accumulate. The default value of this bit is 0.
Data Sheet ADE7763 INTERRUPT STATUS REGISTER (0x0B), RESET INTERRUPT STATUS REGISTER (0x0C), INTERRUPT ENABLE REGISTER (0x0A) The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs, the corresponding flag in the interrupt status register is set to logic high. If the enable bit for this flag is Logic 1 in the interrupt enable register, the IRQ logic output will go active low.
ADE7763 Data Sheet CH1OS REGISTER (0x0D) The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch the digital integrator on and off in Channel 1, and Bits 0 to 5 indicate the amount of offset correction in Channel 1. Table 13 summarizes the function of this register. Table 13. CH1OS Register Bit Mnemonic OFFSET 6 7 Not Used INTEGRATOR Description The 6 LSBs of the CH1OS register control the amount of dc offset correction in the Channel 1 ADC.
Data Sheet ADE7763 OUTLINE DIMENSIONS 7.50 7.20 6.90 11 20 5.60 5.30 5.00 1 8.20 7.80 7.40 10 0.65 BSC SEATING PLANE 8° 4° 0° COMPLIANT TO JEDEC STANDARDS MO-150-AE 0.95 0.75 0.55 060106-A 0.38 0.22 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 89.
ADE7763 Data Sheet NOTES ©2004–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04481-0-1/13(C) Rev.