Datasheet

ADE7758 Data Sheet
Rev. E | Page 68 of 72
INTERRUPT MASK REGISTER (0x18)
When an interrupt event occurs in the ADE7758, the
IRQ
logic output goes active low if the mask bit for this event is Logic 1 in the
MASK register. The
IRQ
logic output is reset to its default collector open state when the RSTATUS register is read. describes the
function of each bit in the interrupt mask register.
Table 23
Table 23. Function of Each Bit in the Interrupt Mask Register
Bit
Location
Interrupt
Flag
Default
Value Description
0 AEHF 0
Enables an interrupt when there is a change in Bit 14 of any one of the three WATTHR registers,
that is, the WATTHR register is half full.
1 REHF 0
Enables an interrupt when there is a change in Bit 14 of any one of the three VARHR registers,
that is, the VARHR register is half full.
2 VAEHF 0
Enables an interrupt when there is a 0 to 1 transition in the MSB of any one of the three VAHR
registers, that is, the VAHR register is half full.
3 SAGA 0 Enables an interrupt when there is a SAG on the line voltage of the Phase A.
4 SAGB 0 Enables an interrupt when there is a SAG on the line voltage of the Phase B.
5 SAGC 0 Enables an interrupt when there is a SAG on the line voltage of the Phase C.
6 ZXTOA 0 Enables an interrupt when there is a zero-crossing timeout detection on Phase A.
7 ZXTOB 0 Enables an interrupt when there is a zero-crossing timeout detection on Phase B.
8 ZXTOC 0 Enables an interrupt when there is a zero-crossing timeout detection on Phase C.
9 ZXA 0
Enables an interrupt when there is a zero crossing in the voltage channel of Phase A (see the
Zero-Crossing Detection section).
10 ZXB 0
Enables an interrupt when there is a zero crossing in the voltage channel of Phase B (see the
Zero-Crossing Detection section).
11 ZXC 0
Enables an interrupt when there is a zero crossing in the voltage channel of Phase C (see the
Zero-Crossing Detection section).
12 LENERGY 0 Enables an interrupt when the energy accumulations over LINECYC are finished.
13 Reserved 0 Reserved.
14 PKV 0
Enables an interrupt when the voltage input selected in the MMODE register is above the value
in the VPINTLVL register.
15 PKI 0
Enables an interrupt when the current input selected in the MMODE register is above the value
in the IPINTLVL register.
16 WFSM 0 Enables an interrupt when data is present in the WAVEMODE register.
17 REVPAP 0
Enables an interrupt when there is a sign change in the watt calculation among any one of the
phases specified by the TERMSEL bits in the COMPMODE register.
18 REVPRP 0
Enables an interrupt when there is a sign change in the VAR calculation among any one of the
phases specified by the TERMSEL bits in the COMPMODE register.
19 SEQERR 0
Enables an interrupt when the zero crossing from Phase A is followed not by the zero crossing
of Phase C but with that of Phase B.