Datasheet

Data Sheet ADE7758
Rev. E | Page 67 of 72
LINE CYCLE ACCUMULATION MODE REGISTER (0x17)
The functionalities involved the line-cycle accumulation mode in the ADE7758 are defined by writing to the LCYCMODE register.
Table 22 summarizes the functionality of each bit in the LCYCMODE register.
Table 22. LCYCMODE Register
Bit
Location
Bit
Mnemonic
Default
Value
Description
0 LWATT 0
Setting this bit places the watt-hour accumulation registers (AWATTHR, BWATTHR, and CWATTHR
registers) into line-cycle accumulation mode.
1 LVAR 0
Setting this bit places the VAR-hour accumulation registers (AVARHR, BVARHR, and CVARHR registers)
into line-cycle accumulation mode.
2 LVA 0
Setting this bit places the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR registers) into
line-cycle accumulation mode.
3 to 5 ZXSEL 7
These bits select the phases used for counting the number of zero crossings in the line-cycle
accumulation mode. Bit 3, Bit 4, and Bit 5 select Phase A, Phase B, and Phase C, respectively. More than
one phase can be selected for the zero-crossing detection, and the accumulation time is shortened
accordingly.
6 RSTREAD 1
Setting this bit enables the read-with-reset for all the WATTHR, VARHR, and VAHR registers for all three
phases, that is, a read to those registers resets the registers to 0 after the content of the registers have
been read. This bit should be set to Logic 0 when the LWATT, LVAR, or LVA bits are set to Logic 1.
7 FREQSEL 0
Setting this bit causes the FREQ (0x10) register to display the period, instead of the frequency of the
line input.