Datasheet
ADE7758 Data Sheet
Rev. E | Page 58 of 72
As explained earlier, the data write is initiated by a write to the
communications register followed by the data. During a data
write operation to the ADE7758, data is transferred to all on-
chip registers one byte at a time. After a byte is transferred into
the serial port, there is a finite time duration before the content
in the serial port buffer is transferred to one of the ADE7758
on-chip registers. Although another byte transfer to the serial
port can start while the previous byte is being transferred to the
destination register, this second-byte transfer should not finish
until at least 900 ns after the end of the previous byte transfer.
This functionality is expressed in the timing specification t
6
(see
Figure 92). If a write operation is aborted during a byte transfer
(
CS
brought high), then that byte is not written to the destination
register.
Destination registers can be up to 3 bytes wide (see the
Accessing the On-Chip Registers section). Therefore, the first
byte shifted into the serial port at DIN is transferred to the most
significant byte (MSB) of the destination register. If the destination
register is 12 bits wide, for example, a two-byte data transfer
must take place. The data is always assumed to be right justified;
therefore, in this case, the four MSBs of the first byte would be
ignored, and the four LSBs of the first byte written to the ADE7758
would be the four MSBs of the 12-bit word. Figure 93 illustrates
this example.
DIN
SCL
K
CS
t
2
t
3
t
1
t
4
t
5
t
7
t
6
t
8
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
1A6 A4A5 A3 A2 A1 A0 DB7 DB0 DB7 DB0
t
7
04443-091
Figure 92. Serial Interface Write Timing Diagram
SCLK
DIN X X X X DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
04443-092
Figure 93. 12-Bit Serial Write Operation
SCLK
CS
t
1
t
10
t
13
0
A6
A4A5 A3
A2
A1
A0
DB0
DB7
DB0
DB7
DIN
DOUT
t
11
t
12
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
t
9
04443-093
Figure 94. Serial Interface Read Timing Diagram