Datasheet

Data Sheet ADE7758
Rev. E | Page 57 of 72
GLOBAL
INTERRUPT
MASK
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
CLEAR MCU
INTERRUPT
FLAG
READ
STATUS WITH
RESET (0x1A)
ISR ACTION
(BASED ON STATUS CONTENTS)
MCU
INTERRUPT
FLAG SET
PROGRAM
SEQUENCE
t
1
t
2
t
3
JUMP
TO
ISR
JUMP
TO
ISR
IRQ
04443-086
Figure 87. ADE7758 Interrupt Management
STATUS REGISTER CONTENTS
SCLK
DIN
DOUT
READ STATUS REGISTER COMMAND
t
1
CS
0001 000
DB15 DB8 DB7 DB0
1
t
9
t
11
t
12
IRQ
04443-087
Figure 88. ADE7758 Interrupt Timing
COMMUNICATIONS
REGISTER
IN
OUT
IN
OUT
IN
OUT
IN
OUT
IN
OUT
REGISTER NO. 1
REGISTER NO. 2
REGISTER NO. 3
REGISTER NO. n–1
REGISTER NO. n
REGISTER
ADDRESS
DECODE
DIN
DOUT
04443-088
Figure 89. Addressing ADE7758 Registers via the Communications Register
The communications register is an 8-bit, write-only register.
The MSB determines whether the next data transfer operation
is a read or a write. The seven LSBs contain the address of the
register to be accessed (see Table 16).
Figure 90 and Figure 91 show the data transfer sequences for a
read and write operation, respectively.
MULTIBYTE
COMMUNICATIONS REGISTER WRITE
DIN
SCLK
DOUT
READ DATA
ADDRESS0
CS
04443-089
Figure 90. Reading Data from the ADE7758 via the Serial Interface
COMMUNICATIONS REGISTER WRITE
DIN
S
CLK
ADDRESS1
CS
MULTIBYTE READ DATA
04443-090
Figure 91. Writing Data to the ADE7758 via the Serial Interface
On completion of a data transfer (read or write), the ADE7758
once again enters into communications mode, that is, the next
instruction followed must be a write to the communications
register.
A data transfer is completed when the LSB of the ADE7758
register being addressed (for a write or a read) is transferred to
or from the ADE7758.
SERIAL WRITE OPERATION
The serial write sequence takes place as follows. With the
ADE7758 in communications mode and the
CS
input logic low,
a write to the communications register takes place first. The
MSB of this byte transfer must be set to 1, indicating that the
next data transfer operation is a write to the register. The seven
LSBs of this byte contain the address of the register to be written
to. The starts shifting in the register data on the next
falling edge of SCLK. All remaining bits of register data are
shifted in on the falling edge of the subsequent SCLK pulses
(see ).
ADE7758
Figure 92