Datasheet

ADE7758 Data Sheet
Rev. E | Page 44 of 72
START
STEP 1
STEP 1A
ENABLE APCF AND
VARCF PUL SE
OUTPUTS
STEP 2
CLEAR GAIN REGISTERS:
xWG, xVAG, xVARG
SELECT VA FOR
VARCF OUTPUT
CFNUM/VARCFNUM
SET TO CALCULATE
VALUES?
NO YES
ALL
PHASES VA
AND WATT
GAIN CAL?
YES NO
STEP 3
SET UP PULSE
OUTPUT FOR
PHASE A, B, OR C
STEP 5
SET UP SYSTEM
FOR I
TEST
,V
NOM
PF = 1
STEP 6
MEASURE %
ERROR FOR APCF
AND VARCF
STEP 7
CALCULATE AND
WRITE TO
xWG, xVAG
CALCULATE Wh/LSB
AND VAh/LSB
CONSTANTS
SET CFNUM/VARCFNUM
AND CFDEN/VARCFDEN
TO CALCULATED VALUES
STEP 4
END
ALL PHASES
VAR GAIN
CALIBRATED?
YES NO
SELECT VAR
FOR VARCF
OUTPUT
STEP 3
SET UP PULSE
OUTPUT FOR
PHASE A, B, OR C
VARCFNUM/
VARCFDEN
SET TO CALCULATED
VALUES?
NO YES
STEP 5
SET UP SYSTEM
FOR I
TEST
,V
NOM
PF = 0, INDUCTIVE
STEP 6
MEASURE %
ERROR FOR
VARCF
STEP 7
CALCULATE AND
WRITE TO xVARG
CALCULATE
VARh/LSB
CONSTANT
SET
VARCFNUM/VARCFDEN TO
CALCULATED VALUES
STEP 4
04443-077
SELECT PHASE A,
B, ORCFORLINE
PERIOD
MEASUREMENT
Figure 78. Gain Calibration Using Pulse Output
Step 1: Enable the pulse output by setting Bit 2 of the OPMODE
register (0x13) to Logic 0. This bit enables both the APCF and
VARCF pulses.
Step 1a: VAR and VA share the VARCF pulse output.
WAVMODE[7], Address (0x15), should be set to choose
between VAR or VA pulses on the output. Setting the bit to
Logic 1 selects VA. The default is Logic 0 or VARCF pulse
output.
Step 2: Ensure the xWG/xVARG/xVAG are zero.
Step 3: Disable the Phase B and Phase C contribution to the APCF
and VARCF pulses. This is done by the TERMSEL[2:4] bits of
the COMPMODE register (0x16). Setting Bit 2 to Logic 1 and
Bit 3 and Bit 4 to Logic 0 allows only Phase A to be included in
the pulse outputs. Select Phase A, Phase B, or Phase C for a line
period measurement with the FREQSEL[1:0] bits in the MMODE
register (0x14). For example, clearing Bit 1 and Bit 0 selects
Phase A for line period measurement.