Datasheet
Data Sheet ADE7758
Rev. E | Page 33 of 72
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation register
is 0.4 µs (4/CLKIN). With full-scale sinusoidal signals on the
analog inputs and the watt gain registers set to 0x000, the average
word value from each LPF2 is 0xCCCCD (see Figure 65 and
Figure 67). The maximum value that can be stored in the watt-
hr accumulation register before it overflows is 2
15
− 1 or 0x7FFF.
Because the average word value is added to the internal register,
which can store 2
40
− 1 or 0xFF, FFFF, FFFF before it overflows,
the integration time under these conditions with WDIV = 0 is
calculated as
sec0.524s0.4
0xCCCCD
FFFFFFFF,0xFF,
=×=Time (21)
When WDIV is set to a value different from 0, the time before
overflow is scaled accordingly as shown in Equation 22.
Time = Time (WDIV = 0) × WDIV[7:0] (22)
Energy Accumulation Mode
The active power accumulated in each watt-hr accumulation
register (AWATTHR, BWATTHR, or CWATTHR) depends on
the configuration of the CONSEL bits in the COMPMODE
register (Bit 0 and Bit 1). The different configurations are
described in Table 10.
Table 10. Inputs to Watt-Hr Accumulation Registers
CONSEL[1, 0] AWAT THR BWAT THR CWATTHR
00 VA × IA VB × IB VC × IC
01 VA × (IA – IB) 0 VC × (IC – IB)
10 VA × (IA – IB) 0 VC × IC
11 Reserved Reserved Reserved
Depending on the poly phase meter service, the appropriate
formula should be chosen to calculate the active energy. The
American ANSI C12.10 Standard defines the different
configurations of the meter.
Table 11 describes which mode should be chosen in these
different configurations.
Table 11. Meter Form Configuration
ANSI Meter Form CONSEL (d) TERMSEL (d)
5S/13S 3-Wire Delta 0 3, 5, or 6
6S/14S 4-Wire Wye 1 7
8S/15S 4-Wire Delta 2 7
9S/16S 4-Wire Wye 0 7
Active Power Frequency Output
Pin 1 (APCF) of the ADE7758 provides frequency output for
the total active power. After initial calibration during manufac-
turing, the manufacturer or end customer often verifies the
energy meter calibration. One convenient way to verify the
meter calibration is for the manufacturer to provide an output
frequency that is proportional to the energy or active power
under steady load conditions. This output frequency can provide a
simple, single-wire, optically isolated interface to external
calibration equipment. Figure 69 illustrates the energy-to-
frequency conversion in the ADE7758.
INPUT TO BWATTHR
REGISTER
INPUT TO AWATTHR
REGISTER
INPUT TO CWATTHR
REGISTER
DFC
APCF
APCFNUM[11:0]
APCFDEN[11:0]
÷
+
+
+
÷4
04443-068
Figure 69. Active Power Frequency Output
A digital-to-frequency converter (DFC) is used to generate the
APCF pulse output from the total active power. The TERMSEL
bits (Bit 2 to Bit 4) of the COMPMODE register can be used to
select which phases to include in the total power calculation.
Setting Bit 2, Bit 3, and Bit 4 includes the input to the AWATTHR,
BWATTHR, and CWATTHR registers in the total active power
calculation. The total active power is signed addition. However,
setting the ABS bit (Bit 5) in the COMPMODE register enables
the absolute-only mode; that is, only the absolute value of the
active power is considered.
The output from the DFC is divided down by a pair of frequency
division registers before being sent to the APCF pulse output.
Namely, APCFDEN/APCFNUM pulses are needed at the DFC
output before the APCF pin outputs a pulse. Under steady load
conditions, the output frequency is directly proportional to the
total active power. The pulse width of APCF is 64/CLKIN if
APCFNUM and APCFDEN are both equal. If APCFDEN is
greater than APCFNUM, the pulse width depends on APCFDEN.
The pulse width in this case is T × (APCFDEN/2), where T is
the period of the APCF pulse and APCFDEN/2 is rounded to
the nearest whole number. An exception to this is when the
period is greater than 180 ms. In this case, the pulse width is
fixed at 90 ms.
The maximum output frequency (APCFNUM = 0x00 and
APCFDEN = 0x00) with full-scale ac signals on one phase is
approximately 16 kHz.
The
ADE7758 incorporates two registers to set the frequency of
APCF (APCFNUM[11:0] and APCFDEN[11:0]). These are
unsigned 12-bit registers that can be used to adjust the frequency of
APCF by 1/2
12
to 1 with a step of 1/2
12
. For example, if the
output frequency is 1.562 kHz while the contents of APCFDEN
are 0 (0x000), then the output frequency can be set to 6.103 Hz
by writing 0xFF to the APCFDEN register.
If 0 were written to any of the frequency division registers, the
divider would use 1 in the frequency division. In addition, the
ratio APCFNUM/APCFDEN should be set not greater than 1 to
ensure proper operation. In other words, the APCF output
frequency cannot be higher than the frequency on the DFC output.
The output frequency has a slight ripple at a frequency equal to
2× the line frequency. This is due to imperfect filtering of the
instantaneous power signal to generate the active power signal