Datasheet

ADE7758 Data Sheet
Rev. E | Page 26 of 72
SAG LEVEL SET
The contents of the single-byte SAG level register, SAGLVL[0:7],
are compared to the absolute value of Bit 6 to Bit 13 from the
voltage waveform samples. For example, the nominal maximum
code of the voltage channel waveform samples with a full-scale
signal input at 60 Hz is 0x2748 (see the Voltage Channel Sampling
section). Bit 13 to Bit 6 are 0x9D. Therefore, writing 0x9D to the
SAG level register puts the SAG detection level at full scale and
sets the SAG detection to its most sensitive value.
The detection is made when the content of the SAGLVL[7:0]
register is greater than the incoming sample. Writing 0x00 puts
the SAG detection level at 0. The detection of a decrease of an
input voltage is disabled in this case.
PEAK VOLTAGE DETECTION
The ADE7758 can record the peak of the voltage waveform and
produce an interrupt if the current exceeds a preset limit.
Peak Voltage Detection Using the VPEAK Register
The peak absolute value of the voltage waveform within a fixed
number of half-line cycles is stored in the VPEAK register.
Figure 58 illustrates the timing behavior of the peak voltage
detection.
L2
L1
CONTENT OF
VPEAK[7:0]
00 L1 L2 L1
NO. OF HALF
LINE CYCLES
SPECIFIED BY
LINECYC[15:0]
REGISTER
VOLTAGE WAVEFORM
(PHASE SELECTED BY
PEAKSEL[2:4]
IN MMODE REGISTER)
04443-058
Figure 58. Peak Voltage Detection Using the VPEAK Register
Note that the content of the VPEAK register is equivalent to
Bit 6 to Bit 13 of the 16-bit voltage waveform sample. At full-
scale analog input, the voltage waveform sample at 60 Hz is
0x2748. The VPEAK at full-scale input is, therefore, expected to
be 0x9D.
In addition, multiple phases can be activated for the peak
detection simultaneously by setting multiple bits among the
PEAKSEL[2:4] bits in the MMODE register. These bits select
the phase for both voltage and current peak measurements.
Note that if more than one bit is set, the VPEAK and IPEAK
registers can hold values from two different phases, that is, the
voltage and current peak are independently processed (see the
Peak Current Detection section).
Note that the number of half-line cycles is based on counting
the zero crossing of the voltage channel. The ZXSEL[2:0] bits in
the LCYCMODE register determine which voltage channels are
used for the zero-crossing detection (see Table 22). The same
signal is also used for line cycle energy accumulation mode if
activated.
Overvoltage Detection Interrupt
Figure 59 illustrates the behavior of the overvoltage detection.
VPINTLVL[7:0]
READ RSTATUS
REGISTER
PKV INTERRUPT FLAG
(BIT 14 OF STATUS
REGISTER)
PKV RESET LOW
WHEN RSTATUS
REGISTER IS READ
VOLTAGE PEAK WAVEFORM BEING MONITORED
(SELECTED BY PKIRQSEL[5:7] IN MMODE REGISTER)
04443-059
Figure 59. ADE7758 Overvoltage Detection
Note that the content of the VPINTLVL[7:0] register is
equivalent to Bit 6 to Bit 13 of the 16-bit voltage waveform
samples; therefore, setting this register to 0x9D represents
putting the peak detection at full-scale analog input. Figure 59
shows a voltage exceeding a threshold. By setting the PKV flag
(Bit 14) in the interrupt status register, the overvoltage event is
recorded. If the PKV enable bit is set to Logic 1 in the interrupt
mask register, the
IRQ
logic output goes active low (see the
section). Interrupts
Multiple phases can be activated for peak detection. If any of the
active phases produce waveform samples above the threshold,
the PKV flag in the interrupt status register is set. The phase in
which overvoltage is monitored is set by the PKIRQSEL[5:7]
bits in the MMODE register (see Table 19).
PHASE SEQUENCE DETECTION
The ADE7758 has an on-chip phase sequence error detection
interrupt. This detection works on phase voltages and considers
all associated zero crossings. The regular succession of these
zero crossings events is a negative to positive transition on
Phase A, followed by a positive to negative transition on Phase
C, followed by a negative to positive transition on Phase B, and
so on.