Poly Phase Multifunction Energy Metering IC with Per Phase Information ADE7758 Data Sheet FEATURES Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time Reference 2.
ADE7758 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Temperature Measurement ....................................................... 27 General Description ......................................................................... 1 Root Mean Square Measurement............................................. 28 Functional Block Diagram ..............................................................
Data Sheet ADE7758 Changes to Current RMS Calculation Section............................28 Changes to Voltage Channel RMS Calculation Section and Figure 63 ...........................................................................................29 Changes to Table 17 ........................................................................60 Changes to Ordering Guide...........................................................70 7/06—Rev. B to Rev. C Updated Format.........................................
ADE7758 Data Sheet GENERAL DESCRIPTION The ADE7758 has a waveform sample register that allows access to the ADC outputs. The part also incorporates a detection circuit for short duration low or high voltage variations. The voltage threshold levels and the duration (number of half-line cycles) of the variation are user programmable. A zero-crossing detection is synchronized with the zero-crossing point of the line voltage of any of the three phases.
Data Sheet ADE7758 SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter 1, 2 ACCURACY Active Energy Measurement Error (per Phase) Phase Error Between Channels PF = 0.8 Capacitive PF = 0.
ADE7758 Data Sheet Parameter 1, 2 LOGIC OUTPUTS IRQ, DOUT, and CLKOUT Output High Voltage, VOH Output Low Voltage, VOL APCF and VARCF Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY AVDD DVDD AIDD DIDD Specification Unit 4 0.4 V min V max 4 1 V min V max 4.75 5.25 4.75 5.
Data Sheet ADE7758 TIMING DIAGRAMS 200µA 2.1V CL 50pF 1.6mA IOH 04443-002 TO OUTPUT PIN IOL Figure 2. Load Circuit for Timing Specifications t8 CS t6 t3 SCLK t4 t2 A6 1 DIN A5 t7 t7 A4 t5 A3 A2 A1 DB7 A0 MOST SIGNIFICANT BYTE COMMAND BYTE DB0 DB7 DB0 LEAST SIGNIFICANT BYTE 04443-003 t1 Figure 3. Serial Write Timing CS t1 t13 t9 SCLK 0 A6 A5 A4 A3 A2 A1 A0 t12 t11 DOUT DB7 COMMAND BYTE DB0 MOST SIGNIFICANT BYTE Figure 4. Serial Read Timing Rev.
ADE7758 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TA = 25°C, unless otherwise noted. Table 3.
Data Sheet ADE7758 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS APCF 1 24 DOUT DGND 2 23 SCLK DVDD 3 22 DIN AVDD 4 21 CS IAP 5 ADE7758 CLKOUT TOP VIEW 19 CLKIN (Not to Scale) IBP 7 18 IRQ 20 IBN 8 17 VARCF ICP 9 16 VAP ICN 10 15 VBP AGND 11 14 VCP REFIN/OUT 12 13 VN 04443-005 IAN 6 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No.
ADE7758 Pin No. 17 Mnemonic VARCF 18 IRQ 19 CLKIN 20 CLKOUT 21 CS 22 DIN 23 SCLK 24 DOUT Data Sheet Description Reactive Power Calibration Frequency Logic Output. It gives reactive power or apparent power information depending on the setting of the VACF bit of the WAVMODE register. This output is used for operational and calibration purposes. The full-scale output frequency can be scaled by writing to the VARCFNUM and VARCFDEN registers (see the Reactive Power Frequency Output section).
Data Sheet ADE7758 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7758 is defined by Measuremen t Error = Energy Registered by ADE7758 – True Energy True Energy × 100% (1) Phase Error Between Channels The high-pass filter (HPF) and digital integrator introduce a slight phase mismatch between the current and the voltage channel.
ADE7758 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.20 PF = 1 0.4 0.15 0.3 PERCENT ERROR (%) PERCENT ERROR (%) 0.10 0.2 0.1 +25°C 0 –40°C –0.1 –0.2 PF = +0.5, –40°C 0.05 PF = –0.5, +25°C 0 –0.05 PF = +0.5, +85°C PF = +0.5, +25°C –0.10 –0.4 –0.5 0.01 –0.15 04443-006 +85°C 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 04443-009 –0.3 –0.20 0.01 100 Figure 6. Active Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 0.
Data Sheet ADE7758 0.3 0.25 PF = 1 0.20 0.2 0.15 PERCENT ERROR (%) ALL PHASES 0.05 0 –0.05 PHASE B –0.10 PHASE C –0.15 PF = 0, +85°C 0 –0.1 PF = 0, +25°C PF = 0, –40°C 04443-012 –0.2 –0.20 –0.25 0.01 0.1 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 04443-015 PERCENT ERROR (%) PHASE A 0.10 –0.3 0.01 100 Figure 12. APCF Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) Figure 15.
ADE7758 Data Sheet 0.10 0.3 0.08 0.2 5.25V 0.04 PERCENT ERROR (%) 5V 0.02 0 –0.02 –0.04 0 +25°C –0.1 4.75V –0.06 +85°C –0.10 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –0.3 0.01 100 Figure 18. Reactive Energy Error as a Percentage of Reading (Gain = +1) over Supply with Internal Reference and Integrator Off 04443-021 04443-018 –0.2 –0.08 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 21.
Data Sheet ADE7758 0.4 0.8 PF = 0 0.6 0.3 0.4 0.1 0 +25°C –0.1 –0.2 –0.3 0 –0.2 04443-024 +85°C –0.5 0.01 –0.6 PF = 1 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) –1.0 –1.2 0.01 100 Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = +4) over Temperature with Internal Reference and Integrator On 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 100 Figure 27. IRMS Error as a Percentage of Reading (Gain = +1) with Internal Reference and Integrator Off 0.5 0.8 0.4 0.6 0.3 0.
ADE7758 Data Sheet 1.5 21 MEAN: 6.5149 SD: 2.816 18 1.0 15 0.5 +25°C HITS 0 12 9 –0.5 6 +85°C –1.0 04443-030 3 –1.5 0.01 0.1 1 10 PERCENT FULL-SCALE CURRENT (%) 0 100 Figure 30. Apparent Energy Error as a Percentage of Reading (Gain = +1) over Temperature with Internal Reference and Integrator Off 04443-032 PERCENT ERROR (%) –40°C –2 0 2 4 6 8 CH 1 PhB OFFSET (mV) 10 12 Figure 32. Phase B Channel 1 Offset Distribution 12 MEAN: 5.55393 SD: 3.2985 MEAN: 6.69333 SD: 2.
Data Sheet ADE7758 TEST CIRCUITS VDD CURRENT 10µF TRANSFORMER I 100nF 4 RB 3 17 AVDD DVDD VARCF APCF 1 5 IAP 1kΩ 825Ω PS2501-1 1 4 2 3 33nF 1kΩ 6 TO FREQ.
ADE7758 Data Sheet THEORY OF OPERATION V2 This filter prevents aliasing, which is an artifact of all sampled systems. Input signals with frequency components higher than half the ADC sampling rate distort the sampled signal at a frequency below half the sampling rate. This happens with all ADCs, regardless of the architecture.
Data Sheet ADE7758 When in waveform sample mode, one of four output sample rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE register (DTRT[1:0]). The output sample rate can be 26.04 kSPS, 13.02 kSPS, 6.51 kSPS, or 3.25 kSPS. By setting the WFSM bit in the interrupt mask register to Logic 1, the interrupt request output IRQ goes active low when a sample is available. The timing is shown in Figure 40.
ADE7758 Data Sheet 80 DI/DT CURRENT SENSOR AND DIGITAL INTEGRATOR 81 82 The di/dt sensor detects changes in the magnetic field caused by the ac current. Figure 42 shows the principle of a di/dt current sensor. PHASE (Degrees) 83 MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT) 84 85 86 87 88 04443-044 89 90 91 10 04443-042 + EMF (ELECTROMOTIVE FORCE) – INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt) 100 1k FREQUENCY (Hz) 10k Figure 44.
Data Sheet ADE7758 Note that the integrator has a −20 dB/dec attenuation and approximately −90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. However, the di/dt sensor has a 20 dB/dec gain associated with it and generates significant high frequency noise. A more effective antialiasing filter is needed to avoid noise due to aliasing (see the Theory of Operation section).
ADE7758 Data Sheet PHASE CALIBRATION VAP VA TO ACTIVE AND REACTIVE ENERGY CALCULATION Φ GAIN[6:5] ×1, ×2, ×4 + PGA – PHCAL[6:0] TO VOLTAGE RMS CALCULATION AND WAVEFORM SAMPLING ADC LPF1 VN f3dB = 260Hz 50Hz LPF OUTPUT WORD RANGE 0x2797 VA 0V ANALOG INPUT RANGE 0.5V GAIN 0x0 0x2852 0xD869 0x0 60Hz 0xD7AE LPF OUTPUT WORD RANGE 0x2748 04443-049 0x0 0xD8B8 Figure 49.
Data Sheet ADE7758 every time a zero crossing is detected on its associated input. The default value of ZXTOUT is 0xFFFF. If the internal register decrements to 0 before a zero crossing at the corresponding input is detected, it indicates an absence of a zero crossing in the time determined by the ZXTOUT[15:0]. The ZXTOx detection bit of the corresponding phase in the interrupt status register is then switched on (Bit 6 to Bit 8).
ADE7758 Data Sheet 0.20 0.15 PHASE (Degrees) Figure 56 illustrates how the phase compensation is used to remove a 0.1° phase lead in IA of the current channel from the external current transducer. To cancel the lead (0.1°) in the current channel of Phase A, a phase lead must be introduced into the corresponding voltage channel. The resolution of the phase adjustment allows the introduction of a phase lead of 0.104°. The phase lead is achieved by introducing a time advance into VA. A time advance of 4.
Data Sheet ADE7758 IAP PGA1 IA ADC IAN ACTIVE AND REACTIVE ENERGY CALCULATION RANGE OF PHASE CALIBRATION VAP PGA2 VA DIGITAL INTEGRATOR HPF ADC +1.36°, –2.76° @ 50Hz; 0.022°, 0.043° +1.63°, –3.31° @ 60Hz; 0.026°, 0.052° VN 6 0 1 1 1 1 1 0 0 VA 0.1° VA IA APHCAL[6:0] –153.6µs TO +75.6µs VA ADVANCED BY 4.8µs (+0.104 ° @ 60Hz) 0x7E 60Hz 60Hz 04443-056 IA Figure 56. Phase Calibration on Voltage Channels The ADE7758 provides the period or frequency measurement of the line voltage.
ADE7758 Data Sheet SAG LEVEL SET The contents of the single-byte SAG level register, SAGLVL[0:7], are compared to the absolute value of Bit 6 to Bit 13 from the voltage waveform samples. For example, the nominal maximum code of the voltage channel waveform samples with a full-scale signal input at 60 Hz is 0x2748 (see the Voltage Channel Sampling section). Bit 13 to Bit 6 are 0x9D.
Data Sheet ADE7758 On the ADE7758, if the regular succession of the zero crossings presented above happens, the SEQERR bit (Bit 19) in the STATUS register is set (Figure 60). If SEQERR is set in the mask register, the IRQ logic output goes active low (see the Interrupts section). monitor threshold. The power supply and decoupling for the part should be designed such that the ripple at AVDD does not exceed 5 V ± 5% as specified for normal operation.
ADE7758 Data Sheet Current RMS Calculation (4) For example, if the temperature register produces a code of 0x46 at ambient temperature (25°C), and the temperature register currently reads 0x50, then the temperature is 55°C : Temp (°C) = [(0x50 – 0x46) × 3°C/LSB] + 25°C = 55°C Depending on the nominal value of the register, some finite temperature can cause the register to roll over. This should be compensated for in the system master (MCU). The ADE7758 temperature register varies with power supply.
Data Sheet ADE7758 VRMSOS[11:0] Current RMS Offset Compensation IRMS IRMS0 2 16384 IRMSOS Table 7. Approximate IRMS Register Values Integrator Off (d) 1,921,472 1,914,752 Integrator On (d) 2,489,581 2,067,210 28 27 26 + + |X| VAN LPF1 AVRMS[23:0] LPF3 50Hz VOLTAGE SIGNAL–V(t) 0.5 GAIN 50Hz 0x193504 LPF OUTPUT WORD RANGE 0x2797 60Hz 0x0 0xD869 0x0 0x1902BD 60Hz LPF OUTPUT WORD RANGE 0x0 0x2748 0x0 0xD8B8 (9) where IRMS0 is the rms measurement without offset correction.
ADE7758 Data Sheet Voltage RMS Gain Adjust The ADC gain in each phase of the voltage channel can be adjusted for the rms calculation by using the voltage rms gain registers (AVRMSGAIN, BVRMSGAIN, and CVRMSGAIN). The gain of the voltage waveforms before LPF1 is adjusted by writing twos complement, 12-bit words to the voltage rms gain registers. Equation 11 shows how the gain adjustment is related to the contents of the voltage gain register.
Data Sheet ADE7758 Active Power Gain Calibration Note that the average active power result from the LPF output in each phase can be scaled by ±50% by writing to the phase’s watt gain register (AWG, BWG, or CWG). The watt gain registers are twos complement, signed registers and have a resolution of 0.024%/LSB. Equation 16 describes mathematically the function of the watt gain registers.
ADE7758 Data Sheet AWATTOS[11:0] HPF DIGITAL INTEGRATOR I SIGN 26 MULTIPLIER 20 + + 0 40 + % 0x2851EC 0 + 0x00 WDIV[7:0] 0xD7AE14 AVERAGE POWER SIGNAL–P Φ V AWATTHR[15:0] AWG[11:0] LPF2 CURRENT SIGNAL–i(t) 15 2–1 2–2 2–3 2–4 T TOTAL ACTIVE POWER IS ACCUMULATED (INTEGRATED) IN THE ACTIVE ENERGY REGISTER PHCAL[6:0] 0xCCCCD 000x 04443-066 VOLTAGE SIGNAL–v(t) 0x2852 0x00000 TIME (nT) 0xD7AE Figure 67.
Data Sheet ADE7758 The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the watt gain registers set to 0x000, the average word value from each LPF2 is 0xCCCCD (see Figure 65 and Figure 67). The maximum value that can be stored in the watthr accumulation register before it overflows is 215 − 1 or 0x7FFF.
ADE7758 Data Sheet (see the Active Power Calculation section). Equation 14 gives an expression for the instantaneous power signal. This is filtered by LPF2, which has a magnitude response given by Equation 23. 1 2 1+ f Vlt (23) 82 The active power signal (output of the LPF2) can be rewritten as ⎡ ⎤ ⎢ VRMS × IRMS ⎥ p(t ) = VRMS × IRMS − ⎢ ⎥ × cos(4 πf1t ) ⎢ (2 f1 )2 2 ⎥ 1 + ⎢⎣ 8 ⎥⎦ VI – 4π × f1 1 + (24) 2f1 2 × cos(4π × f1 × t) 8 04443-069 H( f ) = E(t) t Figure 70.
Data Sheet ADE7758 The number of zero crossings is specified by the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7758 can accumulate active power for up to 65535 combined zero crossings. Note that the internal zero-crossing counter is always active. By setting the LWATT bit, the first energy accumulation result is, therefore, incorrect.
ADE7758 Data Sheet The phase-shift filter has –90° phase shift when the integrator is enabled and +90° phase shift when the integrator is disabled. In addition, the filter has a nonunity magnitude response. Because the phase-shift filter has a large attenuation at high frequency, the reactive power is primarily for the calculation at line frequency. The effect of harmonics is largely ignored in the reactive power calculation.
Data Sheet ADE7758 Similar to reactive power, the fastest integration time occurs when the VAR gain registers are set to maximum full scale, that is, 0x7FF. The time it takes before overflow can be scaled by writing to the VARDIV register; and, therefore, it can be increased by a maximum factor of 255.
ADE7758 Data Sheet The discrete time sample period (T) for the accumulation register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs, a 90° phase difference between the voltage and the current signal (the largest possible reactive power), and the VAR gain registers set to 0x000, the average word value from each LPF2 is 0xCCCCD. The maximum value that can be stored in the reactive energy register before it overflows is 215 − 1 or 0x7FFF.
Data Sheet ADE7758 When using the line cycle accumulation mode, the RSTREAD bit (Bit 6) of the LCYCMODE register should be set to Logic 0. APPARENT POWER CALCULATION Apparent power is defined as the amplitude of the vector sum of the active and reactive powers. Figure 75 shows what is typically referred to as the power triangle. APPARENT POWER For a pure sinusoidal system, the two approaches should yield the same result. The apparent energy calculation in the ADE7758 uses the arithmetical approach.
ADE7758 Data Sheet Apparent Energy Calculation Similar to active or reactive power accumulation, the fastest integration time occurs when the VAGAIN registers are set to maximum full scale, that is, 0x7FF. When overflow occurs, the content of the VA-hr accumulation registers can roll over to 0 and continue increasing in value. Apparent energy is defined as the integral of apparent power.
Data Sheet ADE7758 Table 14. Inputs to VA-Hr Accumulation Registers CONSEL[1, 0] 00 01 10 11 1 AVAHR1 AVRMS × AIRMS AVRMS × AIRMS AVRMS × AIRMS Reserved BVAHR BVRMS × BIRMS AVRMS + CVRMS/2 × BIRMS BVRMS × BIRMS Reserved CVAHR CVRMS × CIRMS CVRMS × CIRMS CVRMS × CIRMS Reserved AVRMS/BVRMS/CVRMS are the rms voltage waveform, and AIRMS/BIRMS/CIRMS are the rms values of the current waveform.
ADE7758 Data Sheet CALIBRATION Calibration Using Pulse Output A reference meter or an accurate source is required to calibrate the ADE7758 energy meter. When using a reference meter, the ADE7758 calibration output frequencies APCF and VARCF are adjusted to match the frequency output of the reference meter under the same load conditions. Each phase must be calibrated separately in this case.
Data Sheet ADE7758 CALIBRATE IRMS OFFSET START CALIBRATE VRMS OFFSET YES ALL PHASES VA AND WATT GAIN CAL? MUST BE DONE BEFORE VA GAIN CALIBRATION NO SET UP PULSE OUTPUT FOR A, B, OR C YES ALL PHASES GAIN CAL VAR? NO SET UP FOR PHASE A, B, OR C YES ALL PHASES PHASE ERROR CAL? NO CALIBRATE WATT AND VA GAIN @ ITEST, PF = 1 WATT AND VA CAN BE CALIBRATED SIMULTANEOUSLY @ PF = 1 BECAUSE THEY HAVE SEPARATE PULSE OUTPUTS CALIBRATE VAR GAIN @ ITEST, PF = 0, INDUCTIVE SET UP PULSE OUTPUT FOR A, B, O
ADE7758 Data Sheet STEP 1 ENABLE APCF AND VARCF PULSE OUTPUTS START STEP 1A SELECT VA FOR VARCF OUTPUT STEP 2 CLEAR GAIN REGISTERS: xWG, xVAG, xVARG ALL PHASES VA AND WATT GAIN CAL? YES NO STEP 3 SELECT VAR FOR VARCF OUTPUT YES SET UP PULSE OUTPUT FOR PHASE A, B, OR C ALL PHASES VAR GAIN CALIBRATED? NO NO STEP 3 STEP 4 SET UP PULSE OUTPUT FOR PHASE A, B, OR C END CFNUM/VARCFNUM SET TO CALCULATE VALUES? SET CFNUM/VARCFNUM AND CFDEN/VARCFDEN TO CALCULATED VALUES YES STEP 5 SET UP SYSTEM FO
Data Sheet ADE7758 Step 4: Set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kWh ratio. For VAR/VA calibration, set VARCFNUM (0x47) and VARCFDEN (0x48) to the calculated value. where CFREF = APCFEXPECTED = the pulse output of the reference meter. The pulse output frequency with one phase at full-scale inputs is approximately 16 kHz.
ADE7758 Data Sheet Step 5: Calculate xPHCAL. PHASE CALIBRATION USING PULSE OUTPUT The ADE7758 includes a phase calibration register on each phase to compensate for small phase errors. Large phase errors should be compensated by adjusting the antialiasing filters. The ADE7758 phase calibration is a time delay with different weights in the positive and negative direction (see the Phase Compensation section).
Data Sheet ADE7758 STEP 1 ENABLE CF OUTPUTS START STEP 2 CLEAR OFFSET REGISTERS xWATTOS, xVAROS YES ALL PHASES WATT OFFSET CALIBRATED? NO STEP 3 SET UP APCF PULSE OUTPUT FOR PHASE A, B, OR C YES ALL PHASES VAR OFFSET CALIBRATED? STEP 4 SET UP SYSTEM FOR IMIN, VNOM, PF = 1 NO STEP 3 END SET UP VARCF PULSE OUTPUT FOR PHASE A, B, OR C STEP 5 SELECT PHASE FOR LINE PERIOD MEASUREMENT STEP 6 MEASURE % ERROR FOR APCF CALCULATE AND WRITE TO xWATTOS CONFIGURE FREQ[11:0] FOR A LINE PERIOD MEASUREMEN
ADE7758 Data Sheet xVAROS = For AWATTOS, 4 Q= (57) For AVAROS, Q= where Q is defined in Equation 58 and Equation 59. For xWATTOS, Q= CLKIN 1 1 × 25 × 4 2 4 1 202 1 CLKIN × 24 × × 4 2 ⎛ FREQ[11 : 0] ⎞ 4 ⎜ ⎟ 4 ⎝ ⎠ 10 E 6 1 202 1 × 24 × × = 0.01444 2083 4 4 2 4 Calibration Using Line Accumulation (58) For xVAROS, Q= 10E6 1 1 × 25 × = 0.01863 4 2 4 (59) where the FREQ (0x10) register is configured for line period measurements. Step 7: Repeat Step 3 to Step 6 for xVAROS calibration.
Data Sheet ADE7758 Gain Calibration Using Line Accumulation Step 2: Select Phase A, Phase B, or Phase C for a line period measurement with the FREQSEL[1:0] bits in the MMODE register (0x14). For example, clearing Bit 1 and Bit 0 selects Phase A for line period measurement. Gain calibration is used for meter-to-meter gain adjustment, APCF or VARCF output rate calibration, and determining the Wh/LSB, VARh/LSB, and VAh/LSB constant. Step 3: Set up ADE7758 for line accumulation by writing 0xBF to LCYCMODE.
ADE7758 Data Sheet Step 5: Set the LENERGY bit, MASK[12] (0x18), to Logic 1 to enable the interrupt signaling the end of the line cycle accumulation. Step 9b: Calculate the values to be written to the xVAG registers according to the following equation: VAHR EXPECTED = Step 6: Set the test system for ITEST, VNOM, and unity power factor (calibrate watt and VA simultaneously and first). 4 × MC × I TEST × VNOM × AccumTime 1000 × 3600 Step 7: Read the FREQ (0x10) register if the line frequency is unknown.
Data Sheet ADE7758 STEP 1 To set APCFNUM (0x45) and APCFDEN (0x46) to the calculated value to perform a coarse adjustment on the imp/kW-hr ratio, use Equation 45 to Equation 47. APCFNOMINAL = 16 kH z × APCFEXPECTED = SET LCYCMODE, LINECYC AND MASK REGISTERS STEP 2 220 10 × = 0.5415 kHz 500 130 3200 × 10 × 220 1000 × 3600 SET UP SYSTEM FOR ITEST , VNOM, PF = 0.5, INDUCTIVE × cos(θ) = 1.956 Hz STEP 3 RESET STATUS REGISTER ⎛ 541.5 Hz ⎞ ⎟ = 277 APCFDEN = INT⎜ ⎜ 1.
ADE7758 Data Sheet If it is not known, the line period is available in the ADE7758 frequency register, FREQ (0x10). To configure line period measurement, select the phase for period measurement in the MMODE[1:0] and set LCYCMODE[7]. Equation 72 shows how to determine the value that needs to be written to xPHCAL using the period register measurement. xPHCAL = Phase Error × 14804d in the AWATTHR register. This is equivalent to −1.132% error. Error = 14804 2 = −0.01132 = −1.
Data Sheet ADE7758 Power Offset Calibration Using Line Accumulation where: Power offset calibration should be used for outstanding performance over a wide dynamic range (1000:1). Calibration of the power offset is done at or close to the minimum current. The ADE7758 has power offset registers for watts and VAR, xWATTOS (0x39 to 0x3B) and xVAROS (0x3C to 0x3E). Offsets in the VA measurement are compensated by adjusting the rms offset registers (see the Calibration of IRMS and VRMS Offset section).
ADE7758 Data Sheet AWATTOS = 0.161 × 4 54.64 × 10 MHz The low-pass filter used to obtain the rms measurements is not ideal; therefore, it is recommended to synchronize the readings with the zero crossings of the voltage waveform and to average a few measurements when reading the rms registers. × 229 = − 0.088 = 0 Calibration of IRMS and VRMS Offset IRMSOS and VRMSOS are used to cancel noise and offset contributions from the inputs.
Data Sheet ADE7758 Step 1: Set configuration registers for zero crossings on all phases by writing the value 0x38 to the LCYCMODE register (0x17). This sets all of the ZXSEL bits to Logic 1. Step 2: Set the interrupt mask register for zero-crossing detection on all phases by writing 0xE00 to the MASK[0:24] register (0x18). This sets all of the ZX bits to Logic 1. Step 3: Set up the calibration system for one of the two test conditions: ITEST and VNOM, and IFULLSCALE/500 and VFULLSCALE/20.
ADE7758 Data Sheet in the interrupt status register are set irrespective of the state of the mask bits. To determine the source of the interrupt, the MCU should perform a read from the reset interrupt status register with reset. This is achieved by carrying out a read from RSTATUS, Address 0x1A. The IRQ output goes logic high on completion of the interrupt status register read command (see the Interrupt Timing section).
Data Sheet ADE7758 t1 t2 MCU INTERRUPT FLAG SET t3 IRQ GLOBAL INTERRUPT MASK CLEAR MCU INTERRUPT FLAG READ STATUS WITH RESET (0x1A) ISR RETURN GLOBAL INTERRUPT MASK RESET ISR ACTION (BASED ON STATUS CONTENTS) JUMP TO ISR 04443-086 JUMP TO ISR PROGRAM SEQUENCE Figure 87. ADE7758 Interrupt Management CS t1 t9 SCLK DIN 0 0 0 1 0 0 0 1 t11 DOUT t12 DB15 DB8 DB7 DB0 READ STATUS REGISTER COMMAND 04443-087 STATUS REGISTER CONTENTS IRQ Figure 88.
ADE7758 Data Sheet As explained earlier, the data write is initiated by a write to the communications register followed by the data. During a data write operation to the ADE7758, data is transferred to all onchip registers one byte at a time. After a byte is transferred into the serial port, there is a finite time duration before the content in the serial port buffer is transferred to one of the ADE7758 on-chip registers.
Data Sheet ADE7758 SERIAL READ OPERATION During a data read operation from the ADE7758, data is shifted out at the DOUT logic output on the rising edge of SCLK. As was the case with the data write operation, a data read must be preceded with a write to the communications register. With the ADE7758 in communications mode and CS logic low, an 8-bit write to the communications register takes place first. The MSB of this byte transfer must be a 0, indicating that the next data transfer operation is a read.
ADE7758 Data Sheet REGISTERS COMMUNICATIONS REGISTER The communications register is an 8-bit, write-only register that controls the serial data transfer between the ADE7758 and the host processor. All data transfer operations must begin with a write to the communications register. The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed. Table 16 outlines the bit designations for the communications register. Table 16.
Data Sheet ADE7758 Address [A6:A0] 0x0E 0x0F 0x10 Name BVRMS CVRMS FREQ R/W 1 R R R Length 24 24 12 Type 2 S S U Default Value 0 0 0 0x11 TEMP R 8 S 0 0x12 WFORM R 24 S 0 0x13 OPMODE R/W 8 U 4 0x14 MMODE R/W 8 U 0xFC 0x15 WAVMODE R/W 8 U 0 0x16 COMPMODE R/W 8 U 0x1C 0x17 LCYCMODE R/W 8 U 0x78 0x18 Mask R/W 24 U 0 0x19 Status R 24 U 0 0x1A RSTATUS R 24 U 0 0x1B ZXTOUT R/W 16 U 0xFFFF 0x1C LINECYC R/W 16 U 0xFFFF 0x1D SAGCYC R/W
ADE7758 Data Sheet Address [A6:A0] 0x22 Name IPEAK R/W 1 R Length 8 Type 2 U Default Value 0 0x23 Gain R/W 8 U 0 0x24 AVRMSGAIN R/W 12 S 0 0x25 0x26 0x27 BVRMSGAIN CVRMSGAIN AIGAIN R/W R/W R/W 12 12 12 S S S 0 0 0 0x28 BIGAIN R/W 12 S 0 0x29 CIGAIN R/W 12 S 0 0x2A AWG R/W 12 S 0 0x2B 0x2C 0x2D BWG CWG AVARG R/W R/W R/W 12 12 12 S S S 0 0 0 0x2E 0x2F 0x30 BVARG CVARG AVAG R/W R/W R/W 12 12 12 S S S 0 0 0 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A
Data Sheet ADE7758 Address [A6:A0] 0x45 Name APCFNUM R/W 1 R/W Length 16 Type 2 U Default Value 0 0x46 APCFDEN R/W 12 U 0x3F 0x47 VARCFNUM R/W 16 U 0 0x48 VARCFDEN R/W 12 U 0x3F 0x49 to 0x7D 0x7E Reserved − − – − CHKSUM R 8 U − 0x7F Version R 8 U − 1 2 Description Active Power CF Scaling Numerator Register. The content of thisregister is used in the numerator of the APCF output scaling calculation.
ADE7758 Data Sheet OPERATIONAL MODE REGISTER (0x13) The general configuration of the ADE7758 is defined by writing to the OPMODE register. Table 18 summarizes the functionality of each bit in the OPMODE register. Table 18. OPMODE Register Bit Location 0 1 2 3 to 5 Bit Mnemonic DISHPF DISLPF DISCF DISMOD Default Value 0 0 1 0 6 SWRST 0 7 Reserved 0 Description The HPFs in all current channel inputs are disabled when this bit is set.
Data Sheet ADE7758 WAVEFORM MODE REGISTER (0x15) The waveform sampling mode of the ADE7758 is defined by writing to the WAVMODE register. Table 20 summarizes the functionality of each bit in the WAVMODE register. Table 20. WAVMODE Register Bit Location 0 to 1 Bit Mnemonic PHSEL Default Value 0 2 to 4 WAVSEL 0 5 to 6 DTRT 0 7 VACF 0 Description These bits are used to select the phase of the waveform sample.
ADE7758 Data Sheet COMPUTATIONAL MODE REGISTER (0x16) The computational method of the ADE7758 is defined by writing to the COMPMODE register. Table 21 summarizes the functionality of each bit in the COMPMODE register. Table 21. COMPMODE Register Bit Location 0 to 1 Bit Mnemonic CONSEL Default Value 0 2 to 4 TERMSEL 7 5 ABS 0 6 SAVAR 0 7 NOLOAD 0 Description These bits are used to select the input to the energy accumulation registers. CONSEL[1:0] = 11 is reserved.
Data Sheet ADE7758 LINE CYCLE ACCUMULATION MODE REGISTER (0x17) The functionalities involved the line-cycle accumulation mode in the ADE7758 are defined by writing to the LCYCMODE register. Table 22 summarizes the functionality of each bit in the LCYCMODE register. Table 22.
ADE7758 Data Sheet INTERRUPT MASK REGISTER (0x18) When an interrupt event occurs in the ADE7758, the IRQ logic output goes active low if the mask bit for this event is Logic 1 in the MASK register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. Table 23 describes the function of each bit in the interrupt mask register. Table 23.
Data Sheet ADE7758 INTERRUPT STATUS REGISTER (0x19)/RESET INTERRUPT STATUS REGISTER (0x1A) The interrupt status register is used to determine the source of an interrupt event. When an interrupt event occurs in the ADE7758, the corresponding flag in the interrupt status register is set. The IRQ pin goes active low if the corresponding bit in the interrupt mask register is set.
ADE7758 Data Sheet OUTLINE DIMENSIONS 15.60 (0.6142) 15.20 (0.5984) 13 24 7.60 (0.2992) 7.40 (0.2913) 12 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.
Data Sheet ADE7758 NOTES Rev.
ADE7758 Data Sheet NOTES ©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04443-0-10/11(E) Rev.
