Datasheet

REV. A–10–
ADE7757
Typical Connection Diagrams
Figure 7 shows a typical connection diagram for Channel V1. A
shunt is the current sensor selected for this example because of
its low cost compared to other current sensors such as the CT
(current transformer). This IC is ideal for low current meters.
V1P
V1N
C
F
C
F
R
F
R
F
30mV
SHUNT
AGND
PHASE NEUTRAL
Figure 7. Typical Connection for Channel V1
Figure 8 shows a typical connection for Channel V2. Typically,
the ADE7757 is biased around the phase wire, and a resistor
divider is used to provide a voltage signal that is proportional to
the line voltage. Adjusting the ratio of R
A
, R
B
, and R
F
is also a
convenient way of carrying out a gain calibration on a meter.
V2P
V2N
C
F
PHASENEUTRAL
R
F
165mV
C
F
R
F
R
B
R
A
*
*R
A
>> R
B
+ R
F
Figure 8. Typical Connections for Channel V2
POWER SUPPLY MONITOR
The ADE7757 contains an on-chip power supply monitor. The
power supply (V
DD
) is continuously monitored by the ADE7757.
If the supply is less than 4 V, the ADE7757 becomes inactive.
This is useful to ensure proper device operation at power-up
and power-down. The power supply monitor has built in hyster-
esis and filtering that provide a high degree of immunity to false
triggering from noisy supplies.
As can be seen from Figure 9, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is within ± 5%. The
power supply and decoupling for the part should be such that
the ripple at V
DD
does not exceed 5 V ± 5% as specified for
normal operation.
V
DD
5V
4V
0V
TIME
INACTIVE ACTIVE INACTIVE
INTERNAL
ACTIVATION
Figure 9. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 10 illustrates the effect of offsets on the real power calcu-
lation. As can be seen, offsets on Channel V1 and Channel V2
will contribute a dc component after multiplication. Since this
dc component is extracted by the LPF and used to generate the
real power information, the offsets will contribute a constant
error to the real power calculation. This problem is easily avoided
by the built-in HPF in Channel V1. By removing the offsets
from at least one channel, no error component can be generated
at dc by the multiplication. Error terms at the line frequency (␻)
are removed by the LPF and the digital-to-frequency conversion
(see Digital-to-Frequency Conversion section).
The equation below shows how the power calculation is affected
by the dc offsets in the current and voltage channels.
VtVItI
VI
VIVI tIV t
VI
t
OS OS
OS OS OS OS
cos cos
cos cos
cos
ωω
ωω
ω
()
+
{}
×
()
+
{}
=
×
+×+×
()
+×
()
+
×
×
()
2
2
2
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
I
OS
 V
V
OS
 I
V
OS
 I
OS
V  I
2
0
FREQUENCY – RAD/s
Figure 10. Effect of Channel Offset on the Real
Power Calculation