Datasheet

ManualsBrandsANALOG DEVICES ManualsPMICsPMIC - power monitoring Single phase SSOP 24 Surface-mount

Energy Metering IC with Pulse Output

ADE7755

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

High accuracy, surpasses 50 Hz/60 Hz IEC 687/IEC 1036

Less than 0.1% error over a dynamic range of 500 to 1

Supplies active power on the frequency outputs, F1 and F2

High frequency output CF is intended for calibration and

supplies instantaneous active power

Synchronous CF and F1/F2 outputs

Logic output REVP provides information regarding the sign

of the active power

Direct drive for electromechanical counters and 2-phase

stepper motors (F1 and F2)

Programmable gain amplifier (PGA) in the current channel

facilitates usage of small shunts and burden resistors

Proprietary ADCs and DSPs provide high accuracy over large

variations in environmental conditions and time

On-chip power supply monitoring

On-chip creep protection (no load threshold)

On-chip reference 2.5 V ± 8% (30 ppm/°C typical) with

external overdrive capability

Single 5 V supply, low power (15 mW typical)

Low cost CMOS process

GENERAL DESCRIPTION

The ADE7755 is a high accuracy electrical energy measurement

IC. The part specifications surpass the accuracy requirements as

quoted in the IEC 1036 standard.

The only analog circuitry used in the ADE7755 is in the ADCs

and reference circuit. All other signal processing (for example,

multiplication and filtering) is carried out in the digital domain.

This approach provides superior stability and accuracy over

extremes in environmental conditions and over time.

The ADE7755 supplies average active power information on the

low frequency outputs, F1 and F2. These logic outputs can be

used to directly drive an electromechanical counter or interface to

an MCU. The CF logic output gives instantaneous active power

information. This output is intended to be used for calibration

purposes or for interfacing to an MCU.

The ADE7755 includes a power supply monitoring circuit on the

supply pin. The ADE7755 remains in a reset condition until

the supply voltage on AV

reaches 4 V. If the supply falls below

4 V, the ADE7755 resets and no pulse is issued on F1, F2, and CF.

Internal phase matching circuitry ensures that the voltage and

current channels are phase matched whether the HPF in Channel 1

is on or off. An internal no load threshold ensures that the

ADE7755 does not exhibit any creep when there is no load.

The ADE7755 is available in a 24-lead SSOP package.

FUNCTIONAL BLOCK DIAGRAM

POWER

SUPPLY MONITOR

G0 G1

AGND

DGND

RESET

F2F1CFREVPS1S0SCFCLKOUTCLKINREF

IN/OUT

ADE7755

4kΩ

2.5V

REFERENCE

ADC

PGA

×1, ×2, ×8, ×16

V1P

V1N

V2P

V2N

DIGITAL-TO-FREQUENCY

CONVERTER

...110101...

...11011001...

ADC

242220131412181710

21121131516

DCAC/

02896-001

PHASE

CORRECTION

LPF

HPF

SIGNAL

PROCESSING

BLOCK

MULTIPLIER

Figure 1.

U.S. Patents 5,745,323; 5,760,617; 5,862,069; and 5,872,469.

Summary of content (20 pages)

PAGE 1
Energy Metering IC with Pulse Output ADE7755 FEATURES GENERAL DESCRIPTION High accuracy, surpasses 50 Hz/60 Hz IEC 687/IEC 1036 Less than 0.
PAGE 2
ADE7755 TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 13 General Description ......................................................................... 1 Typical Connection Diagrams .................................................. 14 Functional Block Diagram ..............................................................
PAGE 3
ADE7755 SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C. Table 1. Parameter ACCURACY 1, 2 Measurement Error1 on Channel 1 Gain = 1 Gain = 2 Gain = 8 Gain = 16 Phase Error1 Between Channels V1 Phase Lead 37° (PF = 0.8 Capacitive) V1 Phase Lag 60° (PF = 0.5 Inductive) AC Power Supply Rejection1 Output Frequency Variation (CF) Min Degrees Degrees 0.2 % reading ±0.3 % reading ±1 ±7 V kΩ kHz mV % ideal ±0.
PAGE 4
ADE7755 Parameter POWER SUPPLY AVDD Min Typ Max 4.75 5.25 DVDD 4.75 5.25 3 2.5 AIDD DIDD 1 2 3 Unit V V V V mA mA Test Conditions/Comments For specified performance 5 V − 5% 5 V + 5% 5 V − 5% 5 V + 5% Typically 2 mA Typically 1.5 mA See the Terminology section. See the Typical Performance Characteristics section for the plots. Sample tested during initial release and after any redesign or process change that may affect this parameter.
PAGE 5
ADE7755 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3.
PAGE 6
ADE7755 DVDD 1 24 F1 AC/DC 2 23 F2 AVDD 3 22 CF NC 4 21 DGND ADE7755 20 REVP TOP VIEW (Not to Scale) 19 NC 18 CLKOUT V2P 8 17 CLKIN RESET 9 16 G0 REFIN/OUT 10 15 G1 AGND 11 14 S0 SCF 12 13 S1 V1P 5 V1N 6 V2N 7 NC = NO CONNECT 02896-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No.
PAGE 7
ADE7755 Pin No. 17 Mnemonic CLKIN 18 CLKOUT 20 REVP 21 DGND 22 CF 23, 24 F2, F1 Description An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7755. The clock frequency for specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and 33 pF (ceramic) should be used with the gate oscillator circuit.
PAGE 8
ADE7755 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.5 –40°C 0.4 0.3 0.2 0.2 0.1 0.1 ERROR (%) 0.3 +25°C 0 +85°C –0.2 –0.3 0.1 –0.4 1 10 FULL-SCALE CURRENT (%) 100 –0.5 0.01 Figure 4. Error as a % of Reading (Gain = 1) 0.6 –40°C PF = 0.5 0.2 0.1 ERROR (%) +25°C 0 –0.1 +25°C PF = 0.5 –0.2 +85°C –0.2 +25°C PF = 1 0 +85°C PF = 0.5 –0.3 –0.4 PF = 1 GAIN = 2 ON-CHIP REFERENCE 1 10 FULL-SCALE CURRENT (%) 100 –0.6 0.01 02896-005 0.1 Figure 5. Error as a % of Reading (Gain = 2) 0.
PAGE 9
ADE7755 0.4 0.8 0.6 –40°C PF = 0.5 PF = 0.5 GAIN = 8 ON-CHIP REFERENCE –40°C 0.2 0.4 0.2 ERROR (%) ERROR (%) PF = 1 GAIN = 16 EXTERNAL REFERENCE 0.3 +25°C PF = 1 0 +25°C PF = 0.5 –0.2 0.1 +25°C 0 –0.1 +85°C –0.2 +85°C PF = 0.5 –0.3 –0.6 0.1 1 10 FULL-SCALE CURRENT (%) 100 –0.4 0.01 02896-010 –0.8 0.01 Figure 10. Error as a % of Reading (Gain = 8) 0.1 100 1 10 FULL-SCALE CURRENT (%) 02896-013 –0.4 Figure 13.
PAGE 10
ADE7755 16 14 12 30 DISTRIBUTION CHARACTERISTICS NUMBER POINTS: 101 MINIMUM: –9.78871 GAIN = 1 MAXIMUM: 7.2939 TEMPERATURE = 25°C MEAN: –1.73203 STD. DEV: 3.61157 25 20 HITS 10 HITS DISTRIBUTION CHARACTERISTICS NUMBER POINTS: 101 MINIMUM: –2.48959 MAXIMUM: 5.81126 MEAN: –1.26847 GAIN = 8 TEMPERATURE = 25°C STD. DEV: 1.57404 8 6 15 10 4 –9 –3 3 CH1 OFFSET (mV) 9 15 0 –15 Figure 16.
PAGE 11
ADE7755 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7755 is defined by the following formula: Percentage Error = Energy Registered by the ADE7755 − True Energy True Energy ×100% Phase Error Between Channels The high-pass filter (HPF) in Channel 1 has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase compensation network is also placed in Channel 1.
PAGE 12
ADE7755 THEORY OF OPERATION The two ADCs of the ADE7755 digitize the voltage signals from the current and voltage transducers. These ADCs are 16-bit, second-order Σ-Δ with an oversampling rate of 900 kHz. This analog input structure greatly simplifies transducer interfacing by providing a wide dynamic range for direct connection to the transducer and also by simplifying the antialiasing filter design. A programmable gain stage in the current channel further facilitates easy transducer interfacing.
PAGE 13
ADE7755 NONSINUSOIDAL VOLTAGE AND CURRENT The active power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications have some harmonic content. Using the Fourier Transform operation, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content. ∞ (1) h≠0 ANALOG INPUTS where: v(t) is the instantaneous voltage. VO is the average voltage value.
PAGE 14
ADE7755 Channel 2 (Voltage Channel) Cf Rf Cf AGND PHASE NEUTRAL V2 Cf Ra1 +660mV Rb1 V2P VCM PHASE NEUTRAL AGND –660mV TYPICAL CONNECTION DIAGRAMS Figure 26 shows a typical connection diagram for Channel 1. A current transformer (CT) is the current transducer selected for this example. Note that the common-mode voltage for Channel 1 is AGND and is derived by center-tapping the burden resistor to AGND. This provides the complementary analog input signals for V1P and V1N.
PAGE 15
ADE7755 HPF and Offset Effects 0.30 Figure 29 shows the effect of offsets on the active power calculation. An offset on Channel 1 and Channel 2 contributes a dc component after multiplication. Because the dc component is extracted by the LPF, it accumulates as active power. If not properly filtered, dc offsets introduce error to the energy accumulation. This problem is easily avoided by enabling the HPF (that is, the AC/DC pin is set to logic high) in Channel 1.
PAGE 16
MULTIPLIER F2 LPF DIGITAL-TOFREQUENCY I CF LPF TO EXTRACT REAL POWER (DC TERM) V×I 2 F1 CF FREQUENCY RIPPLE AVERAGE FREQUENCY TIME ±10% fOUT TIME COUNTER cos(2ωt) ATTENUATED BY LPF CF REVP1 ω 2ω FREQUENCY (RAD/s) UP/DOWN TIMER 02896-032 0 MCU ADE7755 TIME INSTANTANEOUS ACTIVE POWER SIGNAL (FREQUENCY DOMAIN) 1REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR DIRECTION OF ENERGY FLOW IS NEEDED 02896-033 V FREQUENCY DIGITAL-TOFREQUENCY F1 FREQUENCY ADE7755 Figure 32.
PAGE 17
ADE7755 If the on-chip reference is used, actual output frequencies may vary from device to device due to a reference tolerance of ±8%. TRANSFER FUNCTION Frequency Outputs F1 and F2 The ADE7755 calculates the product of two voltage signals (on Channel 1 and Channel 2) and then low-pass filters this product to extract active power information. This active power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active low pulses.
PAGE 18
ADE7755 Table 8. Maximum Output Frequency on CF SCF 1 0 1 0 1 0 1 0 S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 f1, f2, f3, and f4 (Hz) f1 = 1.7 f1 = 1.7 f2 = 3.4 f2 = 3.4 f3 = 6.8 f3 = 6.8 f4 = 13.6 f4 = 13.6 CF Maximum for AC Signals 128 × F1, F2 = 43.52 Hz 64 × F1, F2 = 21.76 Hz 64 × F1, F2 = 43.52 Hz 32 × F1, F2 = 21.76 Hz 32 × F1, F2 = 43.52 Hz 16 × F1, F2 = 21.76 Hz 16 × F1, F2 = 43.52 Hz 2048 × F1, F2 = 5.
PAGE 19
ADE7755 NO LOAD THRESHOLD The ADE7755 also includes a no load threshold and start-up current feature that eliminates any creep effects in the meter. The ADE7755 is designed to issue a minimum output frequency in all modes except when SCF = 0 and S1 = S0 = 1. The no load detection threshold is disabled in this output mode to accommodate specialized application of the ADE7755. Any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on F1, F2, or CF.
PAGE 20
ADE7755 OUTLINE DIMENSIONS 8.50 8.20 7.90 13 24 5.60 5.30 5.00 1 8.20 7.80 7.40 12 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° COMPLIANT TO JEDEC STANDARDS MO-150-AG 0.95 0.75 0.55 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 34.