Datasheet

REV. 0–6–
ADE7754
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Mnemonic Description
3DV
DD
Digital Power Supply. The supply voltage should be maintained at 5 V ± 5% for specified operation.
This pin should be decoupled to DGND with a 10 µF capacitor in parallel with a ceramic
100 nF capacitor.
4AV
DD
Analog Power Supply. The supply should be maintained at 5 V ± 5% for specified operation. Every
effort should be made to minimize power supply ripple and noise at this pin through the use of
proper decoupling. The TPCs chart the power supply rejection performance. This pin should be to
decoupled AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
5, 6; I
AP
, I
AN
;Analog Inputs for Current Channel. This channel is intended for use with the current transducer
7, 8; I
BP
, I
BN
; is referenced in this document as the current channel. These inputs are fully differential voltage
9, 10 I
CP
, I
CN
inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending
on the gain selections of the internal PGA. See the Analog Inputs section.
All inputs have internal ESD protection circuitry. An overvoltage of ±6 V can be sustained on these
inputs without risk of permanent damage.
11 AGND Analog Ground Reference. Used for ADCs, temperature sensor, and reference. This pin should be
tied to the analog ground plane or the quiet
est ground reference in the system. This quiet
ground reference should be used for all analog
circuitry such as anti-aliasing filters and current
and voltage transducers. To keep ground noise
around the ADE7754 to a minimum, the quiet
ground plane should be connected only to the digital ground plane at one point. It is acceptable to
place the entire device on the analog ground plane.
12 REF
IN/OUT
This pin provides access to the on-chip voltage reference, which has a nominal value of 2.4 V ± 8%
and a typical temperature coefficient of 30 ppm/°C. An external reference source may also be connected
at this pin. In either case, this pin should be decoupled to AGND with a 1 µF ceramic capacitor.
13, 14; V
N
, V
CP
; Analog Inputs for the Voltage Channel. This channel is intended for use with the voltage transducer
15, 16 V
BP
, V
AP
and is referenced as the voltage channel in this document. These inputs are single-ended voltage
inputs with maximum signal level of ±0.5 V with respect to V
N
for specified operation. These
inputs are voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and
±0.125 V, depending on the gain selections of the internal PGA. See the Analog Inputs section.
All inputs have internal ESD protection circuitry. An overvoltage of ±6 V can be sustained on these
inputs without risk of permanent damage.
17 RESET Reset. A logic low on this pin holds the ADCs and digital circuitry (including the serial interface) in
a reset condition.
18 IRQ Interrupt Request Output. This is an active low, open-drain logic output. Maskable interrupts
include active energy register at half level, apparent energy register at half level, and waveform
sampling at up to 26 kSPS. See the Interrupts section.
19 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic
input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT
to provide a clock source for the ADE7754. The clock frequency for specified operation is 10 MHz.
Ceramic load capacitors of 22 pF to 33 pF should be used with the gate oscillator circuit. Refer to
the crystal manufacturer’s data sheet for load capacitance requirements.
20 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the ADE7754. The CLKOUT pin can drive one CMOS load when an external clock is supplied
at CLKIN, or a crystal is used.
21 CS Chip Select. Part of the 4-wire serial interface. This active low logic input allows the ADE7754
to share the serial bus with several other devices. See the Serial Interface section.
22 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK. See
the Serial Interface section.
23 SCLK Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to
this clock. See the Serial Interface section. The SCLK has a Schmidt-trigger input for use with a
clock source that has a slow edge transition time (e.g., opto-isolator outputs).
24 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK.
This logic output is normally in a high impedance state unless it is driving data onto the serial
data bus. See the Serial Interface section.