Datasheet

REV. 0–4–
ADE7754
TIMING CHARACTERISTICS
1, 2
(AV
DD
= DV
DD
= 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz XTAL,
T
MIN
to T
MAX
= –40C to +85C, unless otherwise noted.)
Parameter Spec Unit Test Conditions/Comments
Write Timing
t
1
50 ns (min) CS Falling Edge to First SCLK Falling Edge
t
2
50 ns (min) SCLK Logic High Pulsewidth
t
3
50 ns (min) SCLK Logic Low Pulsewidth
t
4
10 ns (min) Valid Data Setup Time before Falling Edge of SCLK
t
5
5 ns (min) Data Hold Time after SCLK Falling Edge
t
6
400 ns (min) Minimum Time between the End of Data Byte Transfers
t
7
50 ns (min) Minimum Time between Byte Transfers during a Serial Write
t
8
100 ns (min) CS Hold Time after SCLK Falling Edge
Read Timing
t
9
3
4 µs (min) Minimum Time between Read Command (i.e., a Write to Communication
Register) and Data Read
t
10
50 ns (min) Minimum Time between Data Byte Transfers during a Multibyte Read
t
11
4
30 ns (min) Data Access Time after SCLK Rising Edge following a Write to the
Communications Register
t
12
5
100 ns (max) Bus Relinquish Time after Falling Edge of SCLK
10 ns (min)
t
13
5
100 ns (max) Bus Relinquish Time after Rising Edge of CS
10 ns (min)
NOTES
1
Sample tested during initial release and after any redesign or process change
that may affect this parameter. All input signals are specified with tr = tf = 5 ns
(10% to 90%) and timed from a voltage level of 1.6 V.
2
See timing diagrams below and Serial Interface section of this data sheet.
3
Minimum time between read command and data read for all registers except
wavmode register, which is t
9
= 500 ns min.
4
Measured with the load circuit in Figure 1 and defined as the time required for
the output to cross 0.8 V or 2.4 V.
5
Derived from the measured time taken by the data outputs to change 0.5 V
when loaded with the circuit in Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF
capacitor. The time quoted in the timing characteristics is the true bus relin-
quish time of the part and is independent of the bus loading.
TO
OUTPUT
PIN
C
L
50pF
1.6mA
200A
I
OH
I
OL
2.1V
Figure 1. Load Circuit for Timing Specifications
CS
SCLK
DIN
A4
A3 A2
A1
A0
DB7
MOST SIGNIFICANT BYTE
t
1
t
2
t
3
t
4
t
5
t
8
1
DB0 DB7
DB0
t
6
LEAST SIGNIFICANT BYTE
t
7
t
7
0
COMMAND BYTE
A5
Figure 2. Serial Write Timing
CS
SCLK
DIN
A4
A3
A2
A1
A0
t
1
t
11
t
12
t
9
DB7
DOUT
t
13
DB0
DB0
DB7
t
10
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
COMMAND BYTE
A5
0
0
Figure 3. Serial Read Timing