Datasheet
Table Of Contents
- FEATURES
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- TIMING CHARACTERISTICS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- PIN CONFIGURATION
- PIN FUNCTION DESCRIPTIONS
- Typical Performance Characteristics
- TERMINOLOGY
- POWER SUPPLY MONITOR
- ANALOG INPUTS
- ANALOG-TO-DIGITAL CONVERSION
- CURRENT CHANNEL ADC
- VOLTAGE CHANNEL ADC
- ZERO-CROSSING DETECTION
- PERIOD MEASUREMENT
- LINE VOLTAGE SAG DETECTION
- PEAK DETECTION
- TEMPERATURE MEASUREMENT
- PHASE COMPENSATION
- ROOT MEAN SQUARE MEASUREMENT
- ACTIVE POWER CALCULATION
- TOTAL ACTIVE POWER CALCULATION
- ENERGY CALCULATION
- LINE ENERGY ACCUMULATION
- REACTIVE POWER CALCULATION
- TOTAL REACTIVE POWER CALCULATION
- APPARENT POWER CALCULATION
- TOTAL APPARENT POWER CALCULATION
- APPARENT ENERGY CALCULATION
- LINE APPARENT ENERGY ACCUMULATION
- ENERGIES SCALING
- CHECK SUM REGISTER
- SERIAL INTERFACE
- INTERRUPTS
- ACCESSING THE ADE7754 ON-CHIP REGISTERS
- OUTLINE DIMENSIONS
REV. 0
ADE7754
–37–
Measurement Mode Register (0Bh)
The configuration of the period and peak measurements made by the ADE7754 are defined by writing to the MMODE register.
Table XII summarizes the functionality of each bit in the MMODE register.
Table XII. MMODE Register
Bit Bit Default
Location Mnemonic Value Description
0-1 PERDSEL 0 These bits are used to select the source of the measurement of the voltage line period.
Bit 1 Bit 0 Source
00Phase A
01Phase B
10Phase C
11Reserved
2-3 PEAKSEL 0 These bits select the line voltage and current phase used for the PEAK detection. If the
selected line voltage is above the level defined in the PKVLVL register, the PKV flag in the
interrupt status register is set. If the selected current input is above the level defined in the
PKILVL register, the PKI flag in the interrupt status register is set.
Bit 3 Bit 2 Source
00Phase A
01Phase B
10Phase C
11Reserved
4-6 ZXSEL 7 These bits select the phases used for counting the number of zero crossing in the line active
and apparent accumulation modes as well as enabling these phases for the zero-crossing
timeout detection, zero crossing, period measurement, and SAG detection. Bits 4, 5, and 6
select Phase A, Phase B, and Phase C, respectively.
7 Reserved.
Waveform Mode Register (0Ch)
The waveform sampling mode of the ADE7754 is defined by writing to the WAVMODE register. Table XIII summarizes the func-
tionality of each bit in the WAVMODE register.
Table XIII. WAVMODE Register
Bit Bit Default
Location Mnemonic Value Description
0-2 WAVSEL 0 These bits are used to select the source of the waveform sample.
Bit 2 Bit 1 Bit 0 Source
0 00Voltage Phase A
0 01Voltage Phase B
0 10Voltage Phase C
0 11Current Phase A
1 00Current Phase B
1 01Current Phase C
110 or 1 Reserved
3-4 DTRT 0 These bits are used to select the waveform sampling update rate.
Bit 4 Bit 3 Update Rate
0026.0 kSPS (CLKIN/3/128)
0113.0 kSPS (CLKIN/3/256)
106.5 kSPS (CLKIN/3/512)
113.3 kSPS (CLKIN/3/1024)
5 LVARSEL 0 This bit is used to enable the accumulation of the line VAR energy into the LAENERGY register
and of the line active energy into the LVAENERGY register.