Datasheet
Table Of Contents
- FEATURES
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- TIMING CHARACTERISTICS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- PIN CONFIGURATION
- PIN FUNCTION DESCRIPTIONS
- Typical Performance Characteristics
- TERMINOLOGY
- POWER SUPPLY MONITOR
- ANALOG INPUTS
- ANALOG-TO-DIGITAL CONVERSION
- CURRENT CHANNEL ADC
- VOLTAGE CHANNEL ADC
- ZERO-CROSSING DETECTION
- PERIOD MEASUREMENT
- LINE VOLTAGE SAG DETECTION
- PEAK DETECTION
- TEMPERATURE MEASUREMENT
- PHASE COMPENSATION
- ROOT MEAN SQUARE MEASUREMENT
- ACTIVE POWER CALCULATION
- TOTAL ACTIVE POWER CALCULATION
- ENERGY CALCULATION
- LINE ENERGY ACCUMULATION
- REACTIVE POWER CALCULATION
- TOTAL REACTIVE POWER CALCULATION
- APPARENT POWER CALCULATION
- TOTAL APPARENT POWER CALCULATION
- APPARENT ENERGY CALCULATION
- LINE APPARENT ENERGY ACCUMULATION
- ENERGIES SCALING
- CHECK SUM REGISTER
- SERIAL INTERFACE
- INTERRUPTS
- ACCESSING THE ADE7754 ON-CHIP REGISTERS
- OUTLINE DIMENSIONS
REV. 0–36–
ADE7754
Gain Register (18h)
The gain of the analog inputs and the mode of accumulation of the active energies in the ADE7754 are defined by writing to the gain
register. Table X summarizes the functionality of each bit in the gain register.
Table X. GAIN Register
Bit Bit Default
Location Mnemonic Value Description
0-1 PGA1 0 These bits are used to select the gain of the current channels inputs.
Bit 1 Bit 0
00PGA1 = 1
01PGA1 = 2
10PGA1 = 4
00Reserved
2 ABS 0 The sum of the absolute active energies is done in the ANERGY and LAENERGY registers
when this bit is set to Logic 1. The regular sum is done when this bit is set to Logic 0—
default mode.
3 NO LOAD 0The active energy of each phase is not accumulated in the total active energy registers if the
instantaneous active power is lower than the no-load threshold when this bit is set to Logic 0;
this mode is selected by default.
4 RESERVED This is intended for factory testing only and should be left at 0.
5-6 PGA2 0 These bits are used to select the gain of the voltage channels inputs.
Bit 6 Bit 5
00PGA2 = 1
01PGA2 = 2
10PGA2 = 4
00Reserved
7 RESERVED This is intended for factory testing only and should be left at 0.
CFNUM Register (25h)
The CF scaling numerator and the sign of the active energy per phase are defined by writing/reading to the CFNUM register.
Table XI summarizes the functionality of each bit in the CFNUM register.
Table XI. CFNUM Register
Bit Bit Default
Location Mnemonic Value Description
0-Bh CFN 0 CF Scaling Numerator Register. The content of this register is used in the numerator of CF
output scaling.
Ch NEGA 0 The sign of the Phase A instantaneous active power is available in this bit. Logic 0 and Logic 1
correspond to positive and negative active power, respectively. The functionality of this bit is
enabled by setting Bit 5 of the WATMode register to Logic 1. When disabled, NEGA is equal
to its default value.
Dh NEGB 0 The sign of the Phase B instantaneous active power is available in this bit. Logic 0 and Logic 1
correspond to positive and negative active power, respectively. The functionality of this bit is
enabled by setting Bit 4 of the WATMode register to Logic 1. When disabled, NEGB is equal
to its default value.
Eh NEGC 0 The sign of the Phase C instantaneous active power is available in this bit. Logic 0 and Logic 1
correspond to positive and negative active power, respectively. The functionality of this bit is
enabled by setting Bit 3 of the WATMode register to Logic 1. When disabled, NEGC is equal
o its default value.
Fh RESERVED