Datasheet

REV. 0–34–
ADE7754
Table VIII. Register List (continued)
Address Default
[A5:A0] Name R/W* Length Value Description
31h CIrmsOS R/W 12 0 Phase C Current RMS Offset Correction Register.
32h AVrmsOS R/W 12 0 Phase A Voltage RMS Offset Correction Register.
33h BVrmsOS R/W 12 0 Phase B Voltage RMS Offset Correction Register.
34h CVrmsOS R/W 12 0 Phase C Voltage RMS Offset Correction Register.
35h AAPGAIN R/W 12 0 Phase A Active Power Gain Adjust. The active power accumulation of the
Phase A can be calibrated by writing to this register. The calibration range
is ±50% of the nominal full scale of the active power. The resolution of the
gain is 0.0244%/LSB. See the Current Channel ADC Gain Adjust section.
36h BAPGAIN R/W 12 0 Phase B Active Power Gain Adjust.
37h CAPGAIN R/W 12 0 Phase C Active Power Gain Adjust.
38h AVGAIN R/W 12 0 Phase A Voltage RMS Gain. The apparent power accumulation of the
Phase A can be calibrated by writing to this register. The calibration
range is ±50% of the nominal full scale of the apparent power. The
resolution of the gain is 0.0244% / LSB. See the Voltage RMS Gain
Adjust section.
39h BVGAIN R/W 12 0 Phase B Voltage RMS Gain.
3Ah CVGAIN R/W 12 0 Phase C Voltage RMS Gain.
3Bh– Reserved.
3Dh
3Eh CHKSUM R 8 Check Sum Register. The content of this register represents the sum of
all 1s of the latest register read from the SPI port.
3Fh VERSION R 8 1 Version of the Die.
*R/W: Read/Write capability of the register.
R: Read-only register.
R/W: Register that can be both read and written.