Datasheet
Table Of Contents
- FEATURES
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- TIMING CHARACTERISTICS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- PIN CONFIGURATION
- PIN FUNCTION DESCRIPTIONS
- Typical Performance Characteristics
- TERMINOLOGY
- POWER SUPPLY MONITOR
- ANALOG INPUTS
- ANALOG-TO-DIGITAL CONVERSION
- CURRENT CHANNEL ADC
- VOLTAGE CHANNEL ADC
- ZERO-CROSSING DETECTION
- PERIOD MEASUREMENT
- LINE VOLTAGE SAG DETECTION
- PEAK DETECTION
- TEMPERATURE MEASUREMENT
- PHASE COMPENSATION
- ROOT MEAN SQUARE MEASUREMENT
- ACTIVE POWER CALCULATION
- TOTAL ACTIVE POWER CALCULATION
- ENERGY CALCULATION
- LINE ENERGY ACCUMULATION
- REACTIVE POWER CALCULATION
- TOTAL REACTIVE POWER CALCULATION
- APPARENT POWER CALCULATION
- TOTAL APPARENT POWER CALCULATION
- APPARENT ENERGY CALCULATION
- LINE APPARENT ENERGY ACCUMULATION
- ENERGIES SCALING
- CHECK SUM REGISTER
- SERIAL INTERFACE
- INTERRUPTS
- ACCESSING THE ADE7754 ON-CHIP REGISTERS
- OUTLINE DIMENSIONS

REV. 0
ADE7754
–29–
CS
SCLK
DIN
A4
A3 A2
A1
A0
DB7
MOST SIGNIFICANT BYTE
t
1
t
2
t
3
t
4
t
5
t
8
1
DB0 DB7
DB0
t
6
LEAST SIGNIFICANT BYTE
t
7
t
7
0
COMMAND BYTE
A5
Figure 44. Serial Interface Write Timing Diagram
SCLK
DB11
DB10
DB9
DB8
DIN
MOST SIGNIFICANT BYTE
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
LEAST SIGNIFICANT BYTE
X
XX
X
Figure 45. 12-Bit Serial Write Operation
Serial Read Operation
During a data read operation from the ADE7754, data is shifted
out at the DOUT logic output on the rising edge of SCLK. As
was the case with the data write operation, a data read must be
preceded by a write to the communications register.
With the ADE7754 in communications mode and CS logic low,
an 8-bit write to the communications register first takes place.
The MSB of this byte transfer must be a 0, indicating that the
next data transfer operation is a read. The six LSBs of this byte
contain the address of the register to be read. The ADE7754
starts shifting out of the register data on the next rising edge of
SCLK. See Figure 46. At this point, the DOUT logic output
switches from high impedance state and starts driving the data
bus. All remaining bits of register data are shifted out on subsequent
SCLK rising edges. The serial interface enters
communications
mode again as soon as the read has been completed. The DOUT
logic output enters a high impedance state on the falling edge of
the last SCLK pulse. The read operation may be aborted by
bringing the CS logic input high before the data transfer is com-
pleted. The DOUT output enters a high impedance state on the
rising edge of CS.
When an ADE7754 register is addressed for a read operation,
the entire contents of that register are transferred to the serial
port. This allows the ADE7754 to modify its on-chip registers
without the risk of corrupting data during a multibyte transfer.
Note that when a read operation follows a write operation, the
read command (i.e., write to communications register) should
not happen for at least 1 µs after the end of the write operation.
If the read command is sent within 1 µs of the write operation,
the last byte of the write operation may be lost.
CS
SCLK
DIN
A4
A3
A2
A1
A0
t
1
t
11
t
12
t
9
DB7
DOUT
t
13
DB0
DB0
DB7
t
10
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
COMMAND BYTE
A5
0
0
Figure 46. Serial Interface Read Timing Diagram