Datasheet

REV. 0–12–
ADE7754
VOLTAGE CHANNEL ADC
Figure 12 shows the ADC and signal processing chain for the
input VA in voltage channel (which is the same for VB and VC).
V
AP
V
N
ADC
1
1, 2, 4
GAIN[6:5]
VA
VA
0V
0.5V
GAIN
ANALOG
INPUT RANGE
TO ACTIVE AND
REACTIVE ENERGY
CALCULATION
–100% TO +100% FS
16
27E9h
D817h
LPF OUTPUT
WORD RANGE
TO VOLTAGE RMS AND
WAVEFORM SAMPLING
60Hz
60Hz
2838h
D7C8h
50Hz
LPF1
Figure 12. ADC and Signal Processing in Voltage Channel
For energy measurements, the output of the ADC (one bit) is
passed directly to the multiplier and is not filtered. This solution
avoids a wide-bits multiplier and does not affect the accuracy of
the measurement. An HPF is not required to remove any dc
offset since it is only required to remove the offset from one
channel to eliminate errors in the power calculation.
In the voltage channel, the samples may also be routed to the
WFORM register (WAVMODE to select VA, VB, or VC and
sampling frequency). However, before being passed to the wave-
form register, the ADC output is passed through a single-pole,
low-pass filter with a cutoff frequency of 260 Hz. The plots in
Figure 13 show the magnitude and phase response of this filter.
The filter output code of any inputs of the voltage channel
swings between D70Bh (–10,485d) and 28F5h (+10,485d) for
full-scale sine wave inputs. This has the effect of attenuating the
signal. For example, if the line frequency is 60 Hz, the signal at
the output of LPF1 will be attenuated by 3%.
|()| . –.Hf
Hz
Hz
dBs=
+




==
1
1
60
260
0 974 0 2
2
FREQUENCY (Hz)
PHASE (Degrees)
0
–20
–40
–60
–80
10
1
10
2
10
3
(60Hz; –0.2dB)
(60Hz; –13)
0
–10
–20
–30
–40
GAIN (dB)
Figure 13. Magnitude and Phase Response of LPF1
Note that LPF1 does not affect the power calculation because it
is used only in the waveform sample mode and rms calculation.
In waveform sample mode, one of four output sample rates
can be chosen by using Bits 3 and 4 of the WAVMODE regis-
ter. The available output sample rates are 26 kSPS, 13.5 kSPS,
6.5 kSPS, or 3.3 kSPS. The interrupt request output IRQ
signals a new sample availability by going active low. The
voltage waveform register is a twos complement 16-bit register.
Because the waveform register is a 24-bit signed register, the
waveform data from the voltage input is located in the 16 LSB of
the waveform register. The sign of the 16-bit voltage input value
is not extended to the upper byte of the waveform register. The
upper byte is instead filled with zeros. 24-bit waveform samples
are transferred from the ADE7754 one byte (eight bits) at a time,
with the most significant byte shifted out first. The timing is the
same as that for the current channels and is shown in Figure 11.
ZERO-CROSSING DETECTION
The ADE7754 has rising edge zero-crossing detection circuits
for each of voltage channels (V
AP
, V
BP
, and V
CP
). Figure 14
shows how the zero-cross signal is generated from the output of
the ADC of the voltage channel.
V
IRQ
13 DEGREES AT 60Hz
0.95
1.0
READ RSTATUS
V
AP
, V
BP
, V
CP
,
V
N
ADC
1, 2, 4
GAIN[6:5]
V
REFERENCE
LPF1
ZERO
CROSS
TO
MULTIPLIER
–100% TO +100% FS
ZERO-CROSSING
DETECTION
f
–3dB
= 260Hz
1
Figure 14. Zero-Crossing Detection on Voltage Channel
The zero-crossing interrupt is generated from the output of
LPF1, which has a single pole at 260 Hz (CLKIN = 10 MHz).
As a result, there is a phase lag between the analog input signal
of the voltage channel and the output of LPF1. The phase
response of this filter is shown in the Voltage Channel ADC
section. The phase lag response of LPF1 results in a time delay
of approximately 0.6 ms (@ 60 Hz) between the zero crossing
on the analog inputs of voltage channel and the falling of IRQ.
When one phase crosses zero from negative to positive values
(rising edge), the corresponding flag in the interrupt status
register (Bits 7 to 9) is set Logic 1. An active low in the IRQ
output also appears if the corresponding ZX bit in the interrupt
enable register is set to Logic 1.
The flag in the interrupt status register is reset to 0 when the inter-
rupt status register with reset (RSTATUS) is read. Each phase has
its own interrupt flag and enable bit in the interrupt register.