Datasheet

ADE7753
Rev. C | Page 6 of 60
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, T
MIN
to T
MAX
= −40°C to +85°C.
Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with
tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. See Figure 3, Figure 4, and the ADE7753 Serial Interface section.
Table 2.
Parameter Spec Unit Test Conditions/Comments
Write Timing
t
1
50 ns (min)
CS falling edge to first SCLK falling edge.
t
2
50 ns (min) SCLK logic high pulse width.
t
3
50 ns (min) SCLK logic low pulse width.
t
4
10 ns (min) Valid data setup time before falling edge of SCLK.
t
5
5 ns (min) Data hold time after SCLK falling edge.
t
6
4 μs (min) Minimum time between the end of data byte transfers.
t
7
50 ns (min) Minimum time between byte transfers during a serial write.
t
8
100 ns (min)
CS hold time after SCLK falling edge.
Read Timing
t
9
1
4 μs (min) Minimum time between read command (i.e., a write to communication
register) and data read.
t
10
50 ns (min) Minimum time between data byte transfers during a multibyte read.
t
11
30 ns (min) Data access time after SCLK rising edge following a write to the
communications register.
t
12
2
100 ns (max) Bus relinquish time after falling edge of SCLK.
10 ns (min)
t
13
3
100 ns (max)
Bus relinquish time after rising edge of
CS
.
10 ns (min)
1
Minimum time between read command and data read for all registers except waveform register, which is t
9
= 500 ns min.
2
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
3
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
DIN
SCL
K
CS
t
2
t
3
t
1
t
4
t
5
t
7
t
6
t
8
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
1
0
A4A5 A3
A2
A1
A0
DB7
DB0
DB7
DB0
t
7
02875-0-081
Figure 3. Serial Write Timing
SCLK
CS
t
1
t
10
t
13
0
0
A4A5 A3
A2
A1
A0
DB0
DB7
DB0
DB7
DIN
DOUT
t
11
t
11
t
12
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
t
9
02875-0-083
Figure 4. Serial Read Timing