Datasheet

ADE7753
Rev. C | Page 53 of 60
Address Name R/W No. Bits Default Type
1
Description
0x12 WGAIN R/W 12 0x0 S
Power Gain Adjust. This is a 12-bit register. The active power calculation can
be calibrated by writing to this register. The calibration range is ±50% of
the nominal full-scale active power. The resolution of the gain adjust is
0.0244%/LSB —see the Calibrating an Energy Meter Based on the ADE7753
section.
0x13 WDIV R/W 8 0x0 U
Active Energy Divider Register. The internal active energy register is divided
by the value of this register before being stored in the AENERGY register.
0x14 CFNUM R/W 12 0x3F U
CF Frequency Divider Numerator Register. The output frequency on the CF
pin is adjusted by writing to this 12-bit read/write register—see the Energy-
to-Frequency Conversion section.
0x15 CFDEN R/W 12 0x3F U
CF Frequency Divider Denominator Register. The output frequency on the
CF pin is adjusted by writing to this 12-bit read/write register—see the
Energy-to-Frequency Conversion section.
0x16 IRMS R 24 0x0 U Channel 1 RMS Value (Current Channel).
0x17 VRMS R 24 0x0 U Channel 2 RMS Value (Voltage Channel).
0x18 IRMSOS R/W 12 0x0 S Channel 1 RMS Offset Correction Register.
0x19 VRMSOS R/W 12 0x0 S Channel 2 RMS Offset Correction Register.
0x1A VAGAIN R/W 12 0x0 S
Apparent Gain Register. Apparent power calculation can be calibrated by
writing to this register. The calibration range is 50% of the nominal full-
scale real power. The resolution of the gain adjust is 0.02444%/LSB.
0x1B VADIV R/W 8 0x0 U
Apparent Energy Divider Register. The internal apparent energy register is
divided by the value of this register before being stored in the VAENERGY
register.
0x1C LINECYC R/W 16 0xFFFF U
Line Cycle Energy Accumulation Mode Line-Cycle Register. This 16-bit
register is used during line cycle energy accumulation mode to set the
number of half line cycles for energy accumulation—see the Line Cycle
Energy Accumulation Mode section.
0x1D ZXTOUT R/W 12 0xFFF U
Zero-Crossing Timeout. If no zero crossings are detected on Channel 2
within a time period specified by this 12-bit register, the interrupt request
line (IRQ
) is activated—see the section. Zero-Crossing Detection
0x1E SAGCYC R/W 8 0xFF U
Sag Line Cycle Register. This 8-bit register specifies the number of
consecutive line cycles the signal on Channel 2 must be below SAGLVL
before the SAG output is activated—see the Line Voltage Sag Detection
section.
0x1F SAGLVL R/W 8 0x0 U
Sag Voltage Level. An 8-bit write to this register determines at what peak
signal level on Channel 2 the SAG
pin becomes active. The signal must
remain low for the number of cycles specified in the SAGCYC register
before the SAG
pin is activated—see the
section.
Line Voltage Sag Detection
0x20 IPKLVL R/W 8 0xFF U
Channel 1 Peak Level Threshold (Current Channel). This register sets the
level of the current peak detection. If the Channel 1 input exceeds this
level, the PKI flag in the status register is set.
0x21 VPKLVL R/W 8 0xFF U
Channel 2 Peak Level Threshold (Voltage Channel). This register sets the
level of the voltage peak detection. If the Channel 2 input exceeds this
level, the PKV flag in the status register is set.
0x22 IPEAK R 24 0x0 U
Channel 1 Peak Register. The maximum input value of the current channel
since the last read of the register is stored in this register.
0x23 RSTIPEAK R 24 0x0 U
Same as Channel 1 Peak Register except that the register contents are reset
to 0 after read.
0x24 VPEAK R 24 0x0 U
Channel 2 Peak Register. The maximum input value of the voltage channel
since the last read of the register is stored in this register.
0x25 RSTVPEAK R 24 0x0 U
Same as Channel 2 Peak Register except that the register contents are reset
to 0 after a read.
0x26 TEMP R 8 0x0 S
Temperature Register. This is an 8-bit register which contains the result of
the latest temperature conversion—see the Temperature Measurement
section.