Single-Phase Multifunction Metering IC with di/dt Sensor Interface ADE7753 line-voltage period measurement, and rms calculation on the voltage and current. The selectable on-chip digital integrator provides direct interface to di/dt current sensors such as Rogowski coils, eliminating the need for an external analog integrator and resulting in excellent long-term stability and precise phase matching between the current and voltage channels.
ADE7753 TABLE OF CONTENTS Features .............................................................................................. 1 Energy Calculation..................................................................... 29 General Description ......................................................................... 1 Power Offset Calibration ........................................................... 31 Functional Block Diagram ..............................................................
ADE7753 REVISION HISTORY 1/10—Rev. B to Rev C 6/04—Rev. 0 to Rev A Changes to Figure 1........................................................................... 1 Changes to t6 Parameter (Table 2) ................................................... 6 Added Endnote 1 to Table 4............................................................. 9 Changes to Figure 32 ......................................................................16 Changes to Period Measurement Section ....................................
ADE7753 SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. See the plots in the Typical Performance Characteristics section. Table 1. Parameter ENERGY MEASUREMENT ACCURACY Active Power Measurement Error Channel 1 Range = 0.5 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel 1 Range = 0.25 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel 1 Range = 0.
ADE7753 Parameter Channel 2 Signal-to-Noise Plus Distortion Bandwidth (–3 dB) REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Current Source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS RESET, DIN, SCLK, CLKIN, and CS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS SAG and IRQ Output High Voltage, VOH Output Low Voltage, VOL ZX and DOUT Output High Voltage, VOH Outp
ADE7753 TIMING CHARACTERISTICS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. See Figure 3, Figure 4, and the ADE7753 Serial Interface section. Table 2.
ADE7753 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND DVDD to AVDD Analog Input Voltage to AGND, V1P, V1N, V2P, and V2N Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature 20-Lead SSOP, Power Dissipation θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating –0.3 V to +7 V –0.
ADE7753 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7753 is defined by the following formula: Percentage Error = ⎛ Energy Register ADE7753 − True Energy ⎞ ⎜ ⎟ × 100% ⎜ ⎟ True Energy ⎝ ⎠ Phase Error between Channels The digital integrator and the high-pass filter (HPF) in Channel 1 have a non-ideal phase response.
ADE7753 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET 1 20 DIN DVDD 2 19 DOUT AVDD 3 18 SCLK V1P 4 ADE7753 17 CS 16 CLKOUT TOP VIEW V2N 6 (Not to Scale) 15 CLKIN V1N 5 14 IRQ V2P 7 13 SAG AGND 8 12 ZX REFIN/OUT 9 11 CF DGND 10 02875-0-005 Figure 5. Pin Configuration (SSOP Package) Table 4. Pin Function Descriptions Pin No. 1 Mnemonic RESET 2 DVDD 3 AVDD 4, 5 V1P, V1N 6, 7 V2N, V2P 8 AGND 9 REFIN/OUT 10 DGND 11 CF 1 Description Reset Pin for the ADE7753.
ADE7753 Pin No. 12 Mnemonic ZX 13 SAG 14 IRQ 15 CLKIN 16 CLKOUT 17 CS 18 SCLK 19 DOUT 20 DIN 1 Description Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section.
ADE7753 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.3 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE 0.4 0.3 –40°C, PF = 0.5 +85°C, PF = 1 0.1 +25°C, PF = 1 ERROR (%) ERROR (%) 0.2 0.1 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE 0.2 0 –0.1 –0.1 +25°C, PF = 0.5 –0.2 +25°C, PF = 1 0 –40°C, PF = 1 –0.3 –0.2 +85°C, PF = 0.5 –0.4 –0.5 0.1 1 10 FULL-SCALE CURRENT (%) –0.3 0.1 100 1 10 FULL-SCALE CURRENT (%) 02875-0-006 02875-0-010 Figure 6.
ADE7753 0.5 0.35 GAIN = 1 INTEGRATOR OFF EXTERNAL REFERENCE 0.4 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE 0.25 0.3 0.15 0.2 +25°C, PF = 0 0.1 0 ERROR (%) ERROR (%) +25°C, PF = 0 +25°C, PF = 0.5 –0.1 –0.2 0.05 –0.05 –0.15 +85°C, PF = 0.5 –0.3 –40°C, PF = 0.5 +85°C, PF = 0 –40°C, PF = 0 –0.25 –0.4 –0.5 0.1 1 10 FULL-SCALE CURRENT (%) –0.35 0.1 100 1 10 FULL-SCALE CURRENT (%) 02875-0-013 100 02875-0-016 Figure 12.
ADE7753 0.1 1.0 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE 0.8 0.6 0.6 –40°C, PF = 1 0.4 PF = 1 0.2 ERROR (%) ERROR (%) 0.4 0 –0.2 –0.4 PF = 0.5 0.2 0 –0.4 –0.6 –0.8 –0.8 50 25°C, PF = 1 –0.2 –0.6 –0.1 45 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE 0.8 55 LINE FREQUENCY (Hz) 60 85°C, PF = 1 –1.0 0.1 65 1 10 FULL-SCALE CURRENT (%) 02875-0-019 02875-0-023 Figure 18.
ADE7753 3.0 0.8 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE 2.5 GAIN = 1 EXTERNAL REFERENCE 0.6 2.0 0.4 PF = 0.5 0.2 1.0 ERROR (%) ERROR (%) 1.5 0.5 PF = 1 0 0 –0.2 –0.5 –0.4 –1.0 –0.6 –1.5 –0.8 –2.0 45 47 49 51 53 55 57 59 FREQUENCY (Hz) 61 63 1 65 10 FULL-SCALE VOLTAGE 100 02875-0-026 02875-0-029 Figure 24. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On Figure 27.
ADE7753 VDD 10μF I 100nF di/dt CURRENT SENSOR 100Ω 1kΩ 33nF 33nF 100Ω 1kΩ 33nF VDD 33nF 100nF AVDD DVDD RESET DIN V1P DOUT V1N SCLK U1 ADE7753 10μF CURRENT TRANSFORMER 1kΩ TO SPI BUS (USED ONLY FOR CALIBRATION) V2N 33nF 600kΩ 110V 1kΩ CLKIN V2P 33nF SAG V1N SCLK U1 ADE7753 22pF 10μF 100nF TO SPI BUS (USED ONLY FOR CALIBRATION) CS V2N 1kΩ 22pF 33nF 600kΩ 110V NOT CONNECTED 1kΩ CLKIN V2P Y1 3.
ADE7753 THEORY OF OPERATION ANALOG INPUTS Table 5. Maximum Input Signal Levels for Channel 1 The ADE7753 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N is ±0.5 V. In addition, the maximum signal level on analog inputs for V1P/V1N and V2P/ V2N is ±0.5 V with respect to AGND. Max Signal Channel 1 0.5 V 0.25 V 0.125 V 0.0625 V 0.0313 V 0.0156 V 0.
ADE7753 The current and voltage rms offsets can be adjusted with the IRMSOS and VRMSOS registers—see Channel 1 RMS Offset Compensation and Channel 2 RMS Offset Compensation sections. DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION VOS × IOS V× I 2 di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR IOS × V A di/dt sensor detects changes in magnetic field caused by ac current. Figure 35 shows the principle of a di/dt current sensor.
ADE7753 cant high frequency noise, therefore a more effective antialiasing filter is needed to avoid noise due to aliasing—see the Antialias Filter section. –88.0 PHASE (Degrees) –88.5 When the digital integrator is switched off, the ADE7753 can be used directly with a conventional current sensor such as a current transformer (CT) or with a low resistance current shunt. –89.0 ZERO-CROSSING DETECTION –89.5 The ADE7753 has a zero-crossing detection circuit on Channel 2.
ADE7753 The flag in the interrupt status register as well as the IRQ output are reset to their default values when the interrupt status register with reset (RSTSTATUS) is read. Zero-Crossing Timeout The zero-crossing detection also has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 128/CLKIN seconds. The register is reset to its user programmed full-scale value every time a zero crossing is detected on Channel 2.
ADE7753 V2 CHANNEL 2 FULL SCALE VPKLVL[7:0] SAGLVL [7:0] PKV RESET LOW WHEN RSTSTATUS REGISTER IS READ SAG RESET HIGH WHEN CHANNEL 2 EXCEEDS SAGLVL [7:0] SAGCYC [7:0] = 0x04 3 LINE CYCLES PKV INTERRUPT FLAG (BIT 8 OF STATUS REGISTER) SAG 02875-0-043 READ RSTSTATUS REGISTER Figure 43. ADE7753 Sag Detection Figure 43 shows the line voltage falling below a threshold that is set in the sag level register (SAGLVL[7:0]) for three line cycles.
ADE7753 ADE7753 INTERRUPTS Using the ADE7753 Interrupts with an MCU ADE7753 interrupts are managed through the interrupt status register (STATUS[15:0]) and the interrupt enable register (IRQEN[15:0]). When an interrupt event occurs in the ADE7753, the corresponding flag in the status register is set to Logic 1— see the Interrupt Status Register section. If the enable bit for this interrupt in the interrupt enable register is Logic 1, then the IRQ logic output goes active low.
ADE7753 Interrupt Timing The ADE7753 Serial Interface section should be reviewed first before reviewing the interrupt timing. As previously described, when the IRQ output goes low, the MCU ISR must read the interrupt status register to determine the source of the interrupt. When reading the status register contents, the IRQ output is set high on the last falling edge of SCLK of the first byte transfer (read interrupt status register command).
ADE7753 Antialias Filter ADE7753 Reference Circuit Figure 47 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing. Aliasing is an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC, appear in the sampled signal at a frequency below half the sampling rate. Figure 49 illustrates the effect.
ADE7753 2.42V, 1.21V, 0.6V ⋅ 1, ⋅ 2, ⋅ 4, REFERENCE ⋅ 8, ⋅ 16 {GAIN[2:0]} V1P {GAIN[4:3]} HPF DIGITAL INTEGRATOR* ADC 1 PGA1 V1 CURRENT RMS (IRMS) CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION dt V1N CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (50Hz) 50Hz 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV, 15.
ADE7753 CURRENT SIGNAL (i(t)) 0x2851EC IRMSOS[11:0] IRMS(t) 0x00 0xD7AE14 HPF1 CHANNEL 1 217 216 215 0x1C82B3 0x00 sgn 225 226 227 LPF3 + 24 24 IRMS 02875-0-0051 Figure 53. Channel 1 RMS Signal Processing CHANNEL 2 ADC Channel 2 Sampling In Channel 2 waveform sampling mode (MODE[14:13] = 1,1 and WSMP = 1), the ADC output code scaling for Channel 2 is not the same as Channel 1. The Channel 2 waveform sample is a 16-bit word and sign extended to 24 bits.
ADE7753 2.42V ×1, ×2, ×4, REFERENCE ×8, ×16 {GAIN [7:5]} V2P PGA2 V2 ACTIVE AND REACTIVE ENERGY CALCULATION ADC 2 LPF1 V2N ANALOG V1 INPUT RANGE 0.5V, 0.25, 0.125, 62.5mV, 31.25mV 0V 0x2852 0x2581 VRMS CALCULATION AND WAVEFORM SAMPLING (PEAK/SAG/ZX) LPF OUTPUT WORD RANGE 0x0000 0xDAE8 0xD7AE 02875-0-054 Figure 55.
ADE7753 from these measurements. If the voltage rms offset register does not have enough range, the CH2OS register can also be used. V1P HPF 24 PGA1 V1 ADC 1 V1N PHASE COMPENSATION LPF2 24 V2P 1 PGA2 V2 DELAY BLOCK 2.24µs/LSB ADC 2 V2N 5 Rev. C | Page 27 of 60 CHANNEL 2 DELAY REDUCED BY 4.48µs (0.1°LEAD AT 60Hz) 0Bh IN PHCAL [5.0] V2 V1 PHCAL [5:0] --100µs TO +34µs 0.1° V1 60Hz 60Hz 02875-0-056 Figure 57. Phase Calibration 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.
ADE7753 0.4 the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 61. 0.3 ERROR (%) 0.2 INSTANTANEOUS POWER SIGNAL 0.1 p(t) = v×i-v×i×cos(2ωt) 0x19999A 0.0 ACTIVE REAL POWER SIGNAL = v × i –0.1 –0.2 VI 0xCCCCD –0.3 –0.4 54 56 58 60 62 FREQUENCY (Hz) 64 66 0x00000 02875-0-059 CURRENT i(t) = 2×i×sin(ωt) Figure 60.
ADE7753 APOS[15:0] CURRENT CHANNEL WDIV[7:0] AENERGY [23:0] LPF2 + 23 + VOLTAGE CHANNEL 0 UPPER 24 BITS ARE ACCESSIBLE THROUGH AENERGY[23:0] REGISTER % WGAIN[11:0] 48 0 ACTIVE POWER SIGNAL 4 CLKIN WAVEFORM REGISTER VALUES OUTPUT LPF2 T OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL ACTIVE ENERGY REGISTER TIME (nT) 02875-0-063 Figure 63.
ADE7753 APOS [15:0] HPF sgn 26 25 I CURRENT SIGNAL – i(t) LPF2 24 + FOR WAVEF0RM SAMPLING 24 2-6 2-7 2-8 0x19999 + 32 FOR WAVEFORM ACCUMULATIOIN MULTIPLIER 1 V VOLTAGE SIGNAL– v(t) INSTANTANEOUS POWER SIGNAL – p(t) 0xCCCCD WGAIN[11:0] 0x19999A 0x000000 02875-0-064 Figure 65. Active Power Signal Processing The ADE7753 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal nonreadable 49-bit energy register.
ADE7753 0xFFFF,FFFF,FFFF before it overflows. The integration time under these conditions with WDIV = 0 is calculated as follows: Time = 0 xFFFF, FFFF, FFFF × 1.12 μs = 375.8 s = 6.26 min(15) 0 xCCCCD When WDIV is set to a value different from 0, the integration time varies, as shown in Equation 16. Time = TimeWDIV =0 × WDIV (16) POWER OFFSET CALIBRATION The ADE7753 also incorporates an active power offset register (APOS[15:0]).
ADE7753 a lower output frequency at CF for calibration can significantly reduce the ripple. Also, averaging the output frequency by using a longer gate time for the counter achieves the same results. From Equation 19 it can be seen that there is a small ripple in the energy calculation due to a sin(2 ωt) component. This is shown graphically in Figure 68. The active energy calculation is shown by the dashed straight line and is equal to V × I × t.
ADE7753 LINE CYCLE ENERGY ACCUMULATION MODE In line cycle energy accumulation mode, the energy accumulation of the ADE7753 can be synchronized to the Channel 2 zero crossing so that active energy can be accumulated over an integral number of half line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation.
ADE7753 90°. The resulting waveform is called the instantaneous reactive power signal. Equation 25 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by +90°. v(t) = 2V sin(ωt + θ) i(t) = 2 I sin(ωt ) The average reactive power over an integral number of lines (n) is given in Equation 26. 1 RP = nT (23) π i ′(t ) = 2 I sin⎛⎜ ωt + ⎞⎟ 2⎠ ⎝ ∫ Rp(t ) dt = VI sin(θ ) (26) 0 where: T is the line cycle period.
ADE7753 The features of the line reactive energy accumulation are the same as the line active energy accumulation. The number of half line cycles is specified in the LINECYC register. LINECYC is an unsigned 16-bit register. The ADE7753 can accumulate reactive power for up to 65535 combined half cycles. At the end of an energy calibration cycle, the CYCEND flag in the interrupt status register is set. If the CYCEND mask bit in the interrupt mask register is enabled, the IRQ output also goes active low.
ADE7753 VAENERGY [23:0] compensation in the apparent power signal processing. The offset compensation of the apparent power measurement is done by calibrating each individual rms measurement. 23 APPARENT ENERGY CALCULATION 0 48 0 The apparent energy is given as the integral of the apparent power.
ADE7753 overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows: LINE APPARENT ENERGY ACCUMULATION 0 xFFFF, FFFF, FFFF Time = × 1.2 μs = 888 s = 12.52 min(32) 0 xD 055 When VADIV is set to a value different from 0, the integration time varies, as shown in Equation 33. Time = TimeWDIV = 0 × VADIV (33) The ADE7753 is designed with a special apparent energy accumulation mode, which simplifies the calibration process.
ADE7753 ENERGIES SCALING The ADE7753 provides measurements of active, reactive, and apparent energies. These measurements do not have the same scaling and thus cannot be compared directly to each other. Table 10. Energies Scaling PF = 1 Integrator On at 50 Hz Active Wh Reactive 0 Apparent Wh × 0.848 Integrator Off at 50 Hz Active Wh Reactive 0 Apparent Wh × 0.848 Integrator On at 60 Hz Active Wh Reactive 0 Apparent Wh × 0.827 Integrator Off at 60 Hz Active Wh Reactive 0 Apparent Wh × 0.
ADE7753 AENERGYexpected = AENERGYnominal × ⎛⎜1 + Watt Gain The first step of calibrating the gain is to define the line voltage, base current and the maximum current for the meter. A meter constant needs to be determined for CF, such as 3200 imp/kWh or 3.2 imp/Wh. Note that the line voltage and the maximum current scale to half of their respective analog input ranges in this example.
ADE7753 ⎛ CFIB(nominal ) CFDEN = INT ⎜ ⎜ CFIB(expected ) ⎝ ⎞ ⎟ −1 ⎟ ⎠ For this example: (44) 958 ⎞ CFDEN = INT ⎛⎜ ⎟ − 1 = (490 − 1) = 489 ⎝ 1.9556 ⎠ This value for CFDEN should be loaded into each meter before calibration. The WGAIN and WDIV registers can then be used to finely calibrate the CF output. The following sections explain how to calibrate a meter based on ADE7753 when using a reference meter or an accurate source.
ADE7753 The nominal LAENERGY reading, LAENERGYIB(nominal), is the LAENERGY reading with the test current applied. The expected LAENERGY reading is calculated from the following equation: CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER ADDR. 0x15 = CFDEN LAENERGYIB(expected) = ⎛ ⎞ ⎜ CFIB(expected ) × Accumulation Time(s) ⎟ ⎟ INT ⎜ CFNUM + 1 ⎜ ⎟ × WDIV ⎜ ⎟ CFDEN + 1 ⎝ ⎠ SET ITEST = Ib, VTEST = VNOM, PF = 1 SET HALF LINECYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR.
ADE7753 LAENERGYIB(expected) = INT (CFIB (expected ) × LINECYC IB / 2 × PERIOD × 8 / CLKIN × (CFDEN + 1)) The calculated Wh/LSB ratio for the active energy register, using Equation 39 is 6.378 × 10−4: 1 ( 489 + 1) −4 Wh LSB = 3.200 imp/Wh = 6.378 × 10 Minimum Current: Load at Minimum Current: CF Error at Minimum Current: CF Numerator: CF Denominator: Clock Frequency: Using Equation 49, APOS is calculated to be −522 for this example.
ADE7753 Calibrating Watt Offset with an Accurate Source Example LAENERGYIMIN(nominal) = 1395 Figure 83 is the flowchart for watt offset calibration with an accurate source. The LAENERGYexpected at IMIN is 1370 using Equation 53. LAENERGYIMIN(expected) = SET ITEST = IMIN, VTEST = VNOM, PF = 1 ⎛I LINECYCI MIN INT ⎜⎜ MIN × LAENERGY IB(expected ) × LINECYC IB ⎝ IB SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C LAENERGYIMIN(expected) = 0.04 35700 ⎞ × 19186 × INT ⎛⎜ ⎟ = INT (1369.
ADE7753 Phase Calibration SET ITEST = Ib, VTEST = VNOM, PF = 0.5 The PHCAL register is provided to remove small phase errors. The ADE7753 compensates for phase error by inserting a small time delay or advance on the voltage channel input. Phase leads up to 1.84° and phase lags up to 0.72° at 50 Hz can be corrected. The error is determined by measuring the active energy at IB and two power factors, PF = 1 and PF =0.5 inductive.
ADE7753 Calibrating Phase with an Accurate Source Example LAENERGYIB, PF With an accurate source, line cycle accumulation is a good method of calibrating phase error. The value of LAENERGY must be obtained at two power factors, PF = 1 and PF = 0.5 inductive. = .5 = 9613 The error using Equation 56 is 9613 − 19186 Error = SET ITEST = Ib, VTEST = VNOM, PF = 0.5 19186 2 = 0.0021 2 ⎛ 0.0021 ⎞ Phase Error (°) = −Arcsin ⎜⎜ ⎟ = −0.07° 3 ⎟⎠ ⎝ SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR.
ADE7753 Apparent Energy Voltage rms compensation is done after the LPF3 filter (see Figure 56). VRMS = VRMS0 + VRMSOS (64) Apparent energy gain calibration is provided for both meter-tometer gain adjustment and for setting the VAh/LSB constant. where: VAENERGY = VRMS0 is the rms measurement without offset correction. VRMS is linear from full-scale to full-scale/20. VAENERGYinitial × To calibrate the offset, two VRMS measurements are required, for example, at Vnominal and Vnominal/10.
ADE7753 CALCULATE CFDEN VALUE FOR DESIGN WRITE CFDEN VALUE TO CFDEN REGISTER ADDR. 0x15 = CFDEN SET ITEST = Ib, VTEST = VNOM, PF = 1 SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C SET MODE FOR LINE CYCLE ACCUMULATION ADDR. 0x09 = 0x0080 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR. 0x0A = 0x04 RESET THE INTERRUPT STATUS READ REGISTER ADDR. = 0x0C INTERRUPT? NO YES RESET THE INTERRUPT STATUS READ REGISTER ADDR.
ADE7753 The impulse/LSB ratio used to convert the value in the LVARENERGY register into a pulse output can be expressed in terms of impulses/VARh and VARh/LSB. imp/LSB = imp / VARh × VARh / LSB = VARCFIB (expected ) VARCFnominal VARCFIB(expected) = VARConstant (imp / VARh) × Vnominal × I b 3600 s/h VARCFIB(nominal) = × sin(ϕ) LVARENERGYIB × PERIOD 50 Hz Accumulation time(s) × PERIOD (73) (74) (75) where the accumulation time is calculated from Equation 37.
ADE7753 ADE7753 SERIAL INTERFACE All ADE7753 functionality is accessible via several on-chip registers—see Figure 89. The contents of these registers can be updated or read using the on-chip serial interface. After poweron or toggling the RESET pin low or a falling edge on CS, the ADE7753 is placed in communications mode. In communications mode, the ADE7753 expects a write to its communications register.
ADE7753 ADE7753 Serial Write Operation The serial write sequence takes place as follows. With the ADE7753 in communications mode (i.e., the CS input logic low), a write to the communications register first takes place. The MSB of this byte transfer is a 1, indicating that the data transfer operation is a write. The LSBs of this byte contain the address of the register to be written to. The ADE7753 starts shifting in the register data on the next falling edge of SCLK.
ADE7753 ADE7753 Serial Read Operation During a data read operation from the ADE7753, data is shifted out at the DOUT logic output on the rising edge of SCLK. As is the case with the data write operation, a data read must be preceded with a write to the communications register. high impedance state on the falling edge of the last SCLK pulse. The read operation can be aborted by bringing the CS logic input high before the data transfer is complete.
ADE7753 ADE7753 REGISTERS Table 12. Summary of Registers by Address Type 1 Address Name R/W No.
ADE7753 Type 1 Address Name R/W No.
ADE7753 Type 1 Address Name R/W No. Bits Default 0x27 PERIOD R 16 0x0 U 0x28– 0x3C 0x3D 0x3E Period of the Channel 2 (Voltage Channel) Input Estimated by ZeroCrossing Processing. The MSB of this register is always zero. Reserved. TMODE CHKSUM R/W R 8 6 – 0x0 U U 0x3F DIEREV R 8 – U Test Mode Register. Checksum Register. This 6-bit read-only register is equal to the sum of all the ones in the previous read—see the ADE7753 Serial Read Operation section. Die Revision Register.
ADE7753 ADE7753 REGISTER DESCRIPTIONS All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the communications register and then transferring the register data. A full description of the serial interface protocol is given in the ADE7753 Serial Interface section. COMMUNICATIONS REGISTER The communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753 and the host processor.
ADE7753 Bit Location 14, 13 Bit Mnemonic WAVSEL1, 0 Default Value 00 Description These bits are used to select the source of the sampled data for the waveform register. WAVSEL1, 0 0 0 15 POAM 0 Length 0 1 Source 24 bits active power signal (output of LPF2) Reserved 1 0 24 bits Channel 1 1 1 24 bits Channel 2 Writing Logic 1 to this bit allows only positive active power to be accumulated in the ADE7753.
ADE7753 INTERRUPT STATUS REGISTER (0x0B), RESET INTERRUPT STATUS REGISTER (0x0C), INTERRUPT ENABLE REGISTER (0x0A) The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs in the ADE7753, the corresponding flag in the interrupt status register is set to logic high. If the enable bit for this flag is Logic 1 in the interrupt enable register, the IRQ logic output goes active low.
ADE7753 CH1OS REGISTER (0x0D) The CH1OS register is an 8-bit, read/write enabled register. The MSB of this register is used to switch on/off the digital integrator in Channel 1, and Bits 0 to 5 indicates the amount of the offset correction in Channel 1. Table 16 summarizes the function of this register. Table 16. CH1OS Register Bit Location 0 to 5 Bit Mnemonic OFFSET 6 7 Not Used INTEGRATOR Description The six LSBs of the CH1OS register control the amount of dc offset correction in Channel 1 ADC.
ADE7753 OUTLINE DIMENSIONS 7.50 7.20 6.90 11 20 5.60 5.30 5.00 1 8.20 7.80 7.40 10 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150-AE 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Figure 98.
ADE7753 NOTES ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02875-0-1/10(C) Rev.
