Datasheet

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Rev. B | Page 90 of 152

Mnemonic Description Bytes Cycles

JNC rel Jump on carry equal to 0 2 3

JZ rel Jump on accumulator = 0 2 3

JNZ rel Jump on accumulator ≠ 0 2 3

DJNZ Rn,rel Decrement register, JNZ relative 2 3

LJMP Long jump unconditional 3 4

LCALL addr16 Long jump to subroutine 3 4

JB bit,rel Jump on direct bit = 1 3 4

JNB bit,rel Jump on direct bit = 0 3 4

JBC bit,rel Jump on direct bit = 1 and clear 3 4

CJNE A,dir,rel Compare A, direct JNE relative 3 4

CJNE A,#data,rel Compare A, immediate JNE relative 3 4

CJNE Rn,#data,rel Compare register, immediate JNE relative 3 4

CJNE @Ri,#data,rel Compare indirect, immediate JNE relative 3 4

DJNZ dir,rel Decrement direct byte, JNZ relative 3 4

MISCELLANEOUS

NOP No operation 1 1

READ-MODIFY-WRITE INSTRUCTIONS

Some 8052 instructions read the latch and others read the pin.

The state of the pin is read for instructions that input a port bit.

Instructions that read the latch rather than the pins are the ones

that read a value, possibly change it, and rewrite it to the latch.

Because these instructions involve modifying the port, it is

assumed that the pins being modified are outputs, so the output

state of the pin is read from the latch. This prevents a possible

misinterpretation of the voltage level of a pin. For example, if a

port pin is used to drive the base of a transistor, a 1 is written to

the bit to turn on the transistor. If the CPU reads the same port

bit at the pin rather than the latch, it reads the base voltage of

the transistor and interprets it as Logic 0. Reading the latch

rather than the pin returns the correct value of 1.

The instructions that read the latch rather than the pins are

called read-modify-write instructions and are listed in Table 66.

When the destination operand is a port or a port bit, these

instructions read the latch rather than the pin.

Table 66. Read-Modify-Write Instructions

Instruction Example Description

ANL ANL P0,A Logic AND

ORL ORL P1,A Logic OR

XRL XRL P2,A Logic EX-OR

JBC JBC P1.1,LABEL Jump if bit = 1 and clear bit

CPL CPL P2.0 Complement bit

INC INC P2 Increment

DEC DEC P2 Decrement

DJNZ DJNZ P0,LABEL Decrement and jump if not zero

MOV PX.Y,C

MOV P0.0,C Move carry to Bit Y of Port X

CLR PX.Y

CLR P0.0 Clear Bit Y of Port X

SETB PX.Y

SETB P0.0 Set Bit Y of Port X

These instructions read the port byte (all eight bits), modify the addressed

bit, and write the new byte back to the latch.

INSTRUCTIONS THAT AFFECT FLAGS

Many instructions explicitly modify the carry bit, such as the

MOV C bit and CLR C instructions. Other instructions that

affect status flags are listed in this section.

ADD A, Source

This instruction adds the source to the accumulator. No status

flags are referenced by the instruction.

Table 67. ADD A (Source) Affected Status Flags

Flag Description

Set if there is a carry out of Bit 7. Cleared otherwise.

Used to indicate an overflow if the operands are

unsigned.

Set if there is a carry out of Bit 6 or a carry out of Bit 7,

but not if both are set. Used to indicate an overflow for

signed addition. This flag is set if two positive operands

yield a negative result or if two negative operands yield

a positive result.

AC Set if there is a carry out of Bit 3. Cleared otherwise.

ADDC A, Source

This instruction adds the source and the carry bit to the accu-

mulator. The carry status flag is referenced by the instruction.

Table 68. ADDC A (Source) Affected Flags