Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 83 of 152
Table 58. Program Control SFR (PCON, Address 0x87)
Bit Mnemonic Default Description
7 SMOD 0 Double baud rate control.
[6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation.
Table 59. Data Pointer Low SFR (DPL, Address 0x82)
Bit Mnemonic Default Description
[7:0] DPL 0 These bits contain the low byte of the data pointer.
Table 60. Data Pointer High SFR (DPH, Address 0x83)
Bit Mnemonic Default Description
[7:0] DPH 0 These bits contain the high byte of the data pointer.
Table 61. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83)
Bit Mnemonic Default Description
[15:0] DP 0
These bits contain the 2-byte address of the data pointer. DPTR is a combination of the DPH and DPL
SFRs.
Table 62. Stack Pointer SFR (SP, Address 0x81)
Bit Mnemonic Default Description
[7:0] SP 7 These bits contain the eight LSBs of the pointer for the stack.
Table 63. Configuration SFR (CFG, Address 0xAF)
Bit Mnemonic Default Description
7 Reserved 1 Reserved. This bit should be left set for proper operation.
6 EXTEN 0 Enhanced UART enable bit.
EXTEN Result
0 Standard 8052 UART without enhanced error-checking features.
1
Enhanced UART with enhanced error checking (see the UART Additional
Features section).
5 SCPS 0 Synchronous communication selection bit.
SCPS Result
0 I
2
C port is selected for control of the shared I
2
C/SPI pins and SFRs.
1 SPI port is selected for control of the shared I
2
C/SPI pins and SFRs.
4 MOD38EN 0 38 kHz modulation enable bit.
MOD38EN Result
0 38 kHz modulation is disabled.
1
38 kHz modulation is enabled on the pins selected by the MOD38[7:0]
bits in the extended port configuration SFR (EPCFG, Address 0x9F).
[3:2] Reserved 00 Reserved. These bits should be kept at 0 for proper operation.
[1:0] XREN1, XREN0 01
XREN[1:0] Result
XREN1 OR XREN0 = 1 Enable MOVX instruction to use 256 bytes of extended RAM.
XREN1 AND XREN0 = 0 Disable MOVX instruction.