Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 75 of 152
06353-053
LPF1
+
+
LVAHR[23:0]
LVAHR REGISTER IS
UPDATED EVERY LINCYC
ZERO CROSSING WITH THE
TOTAL APPARENT ENERGY
DURING THAT DURATION
FROM
VOLTAGE CHANNEL
ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION
CALIBR ATI ON
CONTROL
VADIV[7:0]
APPARENT POWER
or I
rms
Figure 78. Line Cycle Apparent Energy Accumulation
ENERGY-TO-FREQUENCY CONVERSION
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 also provide two energy-to-frequency conversions for
calibration purposes. After initial calibration at manufacturing,
the manufacturer or end customer often verifies the energy meter
calibration. One convenient way to do this is for the manufacturer
to provide an output frequency that is proportional to the active
power, reactive power, apparent power, or I
rms
under steady load
conditions. This output frequency can provide a simple single-
wire, optically isolated interface to external calibration equipment.
Figure 79 illustrates the energy-to-frequency conversion in the
ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569.
VAR
*
VA
CFxSEL[1:0]
WATT
VARMSCFCON
*
AVAILABLE ONLY IN THE ADE7569 AND ADE7169
MODE2 REGISTER 0x0C
I
rms
CFx PULSE
OUTPUT
CFxNUM
CFxDEN
÷
DFC
06353-054
Figure 79. Energy-to-Frequency Conversion
Two digital-to-frequency converters (DFC) are used to generate
the pulsed outputs. When WDIV = 0 or 1, the DFC generates a
pulse each time 1 LSB in the energy register is accumulated. An
output pulse is generated when a CFxNUM/CFxDEN number
of pulses is generated at the DFC output. Under steady load
conditions, the output frequency is proportional to the active
power, reactive power, apparent power, or I
rms
, depending on the
CFxSEL bits in the MODE2 register (Address 0x0C).
Both pulse outputs can be enabled or disabled by clearing or
setting the DISCF1 bit (Bit 1) and the DISCF2 bit (Bit 2) in the
MODE1 register (Address 0x0B), respectively.
Both pulse outputs set separate flags in the Interrupt Status 2 SFR
(MIRQSTM, Address 0xDD): CF1 (Bit 6) and CF2 (Bit 7). If the
CF1 enable bit (Bit 6) and CF2 enable bit (Bit 7) in the Interrupt
Enable 2 SFR (MIRQENM, Address 0xDA) are set, the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active
until the CF1 or CF2 status bit is cleared (see the Energy
Measurement Interrupts section).
Pulse Output Configuration
The two pulse output circuits have separate configuration bits
in the MODE2 register (Address 0x0C). Setting the CFxSEL bits
to 0b00, 0b01, or 0b1X configures the DFC to create a pulse
output proportional to active power , reactive power (ADE7169/
ADE7569 only), or apparent power or I
rms
, respectively.
The selection between I
rms
and apparent power is done by the
VARMSCFCON bit in the MODE2 register (Address 0x0C).
With this selection, CF2 cannot be proportional to apparent
power if CF1 is proportional to I
rms
, and CF1 cannot be
proportional to apparent power if CF2 is proportional to I
rms
.
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse
period is longer than 180 ms (5.56 Hz). If the pulse period is
shorter than 180 ms, the duty cycle of the pulse output is 50%.
The pulse output is active low and should be connected to an
LED, as shown in Figure 80.
V
DD
CF
06353-055
Figure 80. CF Pulse Output
The maximum output frequency with ac input signals at
full scale and with CFxNUM = 0x00 and CFxDEN = 0x00
is approximately 21.1 kHz.
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 incorporate two registers per DFC, CFxNUM[15:0]
and CFxDEN[15:0], to set the CFx frequency. These unsigned,
16-bit registers can be used to adjust the CFx frequency to a wide
range of values. These frequency scaling registers are 16-bit
registers that can scale the output frequency by 1/2
16
to 1 with
a step of 1/2
16
.