Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 44 of 152
Address
MADDPT[6:0] Mnemonic R/W
Length
(Bits)
Signed/
Unsigned Default Description
0x25 VARDIV R/W 8 U 0 Sets var energy scaling register.
0x26 VADIV R/W 8 U 0 Sets VA energy scaling register.
0x27 CF1NUM R/W 16 U 0 Sets CF1 numerator register.
0x28 CF1DEN R/W 16 U 0x003F Sets CF1 denominator register.
0x29 CF2NUM R/W 16 U 0 Sets CF2 numerator register.
0x2A CF2DEN R/W 16 U 0x003F Sets CF2 denominator register.
0x3B Reserved 0 This register must be set to its default value for proper operation.
0x3C Reserved 0x0300 This register must be set to its default value for proper operation.
0x3D CALMODE
2
R/W 8 U 0 Set calibration mode.
0x3E Reserved 0 This register must be set to its default value for proper operation.
0x3F Reserved 0 This register must be set to its default value for proper operation.
1
This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.
2
This function is not available in the ADE7566 or ADE7569.
ENERGY MEASUREMENT INTERNAL REGISTER DETAILS
Table 33. MODE1 Register (MODE1, Address 0x0B)
Bit Mnemonic Default Description
7 SWRST 0 Setting this bit resets all of the energy measurement registers to their default values.
6 DISZXLPF 0 Setting this bit disables the zero-crossing low-pass filter.
5 INTE 0 Setting this bit enables the digital integrator for use with a di/dt sensor.
4 SWAPBITS 0 Setting this bit swaps CH1 ADC and CH2 ADC.
3 PWRDN 0 Setting this bit powers down voltage and current ADCs.
2 DISCF2 1 Setting this bit disables Frequency Output CF2.
1 DISCF1 1 Setting this bit disables Frequency Output CF1.
0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels.
Table 34. MODE2 Register (MODE2, Address 0x0C)
Bit Mnemonic Default Description
[7:6] CF2SEL 01 Configuration bits for CF2 output.
CF2SEL Result
00 CF2 frequency is proportional to active power.
01 CF2 frequency is proportional to reactive power.
1
1X CF2 frequency is proportional to apparent power or I
rms
.
[5:4] CF1SEL 00 Configuration bits for CF1 output.
CF1SEL Result
00 CF1 frequency is proportional to active power.
01 CF1 frequency is proportional to reactive power.
1
1X CF1 frequency is proportional to apparent power or I
rms
.
3 VARMSCFCON 0
Configuration bits for apparent power or I
rms
for CF1, CF2 outputs and VA accumulation registers
(VAHR, RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is proportional to
I
rms
, and vice versa.
VARMSCFCON Result
0 If CF1SEL[1:0] = 1X, CF1 is proportional to VA.
If CF2SEL[1:0] = 1X, CF2 is proportional to VA.
1 If CF1SEL[1:0] = 1X, CF1 is proportional to I
rms
.
If CF2SEL[1:0] = 1X, CF2 is proportional to I
rms
.
2 ZXRMS 0 Logic 1 enables update of rms values synchronously to Voltage ZX.