Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 30 of 152
Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)
Bit Bit Address Mnemonic Default Description
7 0xFF FPSR 0
Power supply restored interrupt flag. Set when the V
DD
power supply has been restored.
This occurs when the source of V
SWOUT
changes from V
BAT
to V
DD
.
6 0xFE FPSM 0 PSM interrupt flag. Set when an enabled PSM interrupt condition occurs.
5 0xFD FSAG 0 Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs.
4 0xFC Reserved 0 This bit must be kept at 0 for proper operation.
3 0xFB FVADC
1
0
VDCINADC monitor interrupt flag. Set when V
DCIN
changes by VDCIN_DIFF or when V
DCIN
measurement is ready.
2 0xFA FBAT
1
0 V
BAT
monitor interrupt flag. Set when V
BAT
falls below BATVTH or when V
BAT
measurement is ready.
1 0xF9 FBSO 0 Battery switchover interrupt flag. Set when V
SWOUT
switches from V
DD
to V
BAT.
0 0xF8 FVDCIN
1
0 V
DCIN
monitor interrupt flag. Set when V
DCIN
falls below 1.2 V.
1
This feature is not available in the ADE7116.
Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5)
Bit Mnemonic Default Description
[7:2] Reserved 00 These bits must be kept at 0 for proper operation.
[1:0] BATPRG 00 Control bits for battery switchover.
BATPRG Result
00 Battery switchover enabled on low V
DD
01 Battery switchover enabled on low V
DD
and low V
DCIN
1X Battery switchover disabled
Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4)
Bit Mnemonic Default Description
7 RXFLAG 0 If set, indicates that an Rx edge event triggered wake-up from PSM2.
6 VSWSOURCE 1 Indicates the power supply that is internally connected to V
SWOUT
(0: V
SWOUT
= V
BAT
; 1: V
SWOUT
= V
DD
).
5 VDD_OK 1 If set, indicates that V
DD
power supply is ready for operation.
4 PLL_FLT 0
If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 51) in
the start ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the
PLL_FLT bit.
3 REF_BAT_EN 0
Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in
PSM1 and PSM2 mode.
2 Reserved 0 This bit must be kept at 0 for proper operation.
[1:0] RXPROG 00 Controls the function of the P1.0/RxD pin.
RXPROG Result
00 GPIO
01 RxD with wake-up disabled
11 RxD with wake-up enabled
Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)
Bit Mnemonic Default Description
7 EPSR 0 Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set.
6 Reserved 0 Reserved.
5 ESAG 0 Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set.
4 Reserved 0 This bit must be kept at 0 for proper operation.
3 EVADC
1
0 Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set.
2 EBAT
1
0 Enables a PSM interrupt when the V
BAT
monitor interrupt flag (FBAT) is set.
1 EBSO 0 Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set.
0 EVDCIN
1
0 Enables a PSM interrupt when the V
DCIN
monitor interrupt flag (FVDCIN) is set.
1
This feature is not available in the ADE7116.