Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 141 of 152
I
2
C RECEIVE AND TRANSMIT FIFOS
The I
2
C peripheral has a 4-byte receive FIFO and a 4-byte
transmit FIFO. The buffers reduce the overhead associated with
using the I
2
C peripheral. Figure 115 shows the operation of the
I
2
C receive and transmit FIFOs.
The Tx FIFO can be loaded with four bytes to be transmitted to
the slave at the beginning of a write operation. When the
transmit FIFO is empty, the I
2
C transmit interrupt flag is set,
and the PC vectors to the I
2
C interrupt vector if this interrupt is
enabled. If a new byte is not loaded into the Tx FIFO before it is
needed in the transmit shift register, the communication stops.
An error, such as not receiving an acknowledge, also causes the
communication to terminate. In case of an error during a write
operation, the Tx FIFO is flushed.
The Rx FIFO allows four bytes to be read in from the slave
before the MCU has to read the data. A receive interrupt can
be generated after each byte is received or when the Rx FIFO
is full. If the peripheral is reading from a slave address, the
communication stops when the number of received bytes equals
the number set in the I2CRCT bits. An error, such as not
receiving an acknowledge, also causes the communication to
terminate.
I
2
CTx
4 BYTE FIFO
MOV I
2
CTx, TxDATA1
MOV I
2
CTx, TxDATA2
MOV I
2
CTx, TxDATA3
MOV I
2
CTx, TxDATA4
CODE TO FILL Tx FIFO:
TRANSMIT SHIFT REGISTER
I
2
CRx
RECEIVE SHIFT REGISTER
4 BYTE FIFO
CODE TO READ Rx FIFO:
MOV A, I
2
CRx; RESULT: A = RxDATA1
MOV A, I
2
CRx; RESULT: A = RxDATA2
MOV A, I
2
CRx; RESULT: A = RxDATA3
MOV A, I
2
CRx; RESULT: A = RxDATA4
TxDATA1
TxDATA2
TxDATA3
TxDATA4
RxDATA4
RxDATA3
RxDATA2
RxDATA1
06353-089
Figure 115. I
2
C FIFO Operation