Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 140 of 152
Table 154. I
2
C Interrupt Status Register SFR (SPI2CSTAT, Address 0xEA)
Bit Mnemonic Default Description
7 I2CBUSY 0 This bit is set to Logic 1 when the I
2
C interface is used. When set, the Tx FIFO is emptied.
6 I2CNOACK 0
I
2
C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device
does not send an acknowledgement. The I
2
C communication is stopped after this event.
Write a 0 to this bit to clear it.
5 I2CRxIRQ 0
I
2
C receive interrupt. This bit is set to Logic 1 when the receive FIFO is not empty.
Write a 0 to this bit to clear it.
4 I2CTxIRQ 0
I
2
C Transmit Interrupt. This bit is set to Logic 1 when the transmit FIFO is empty.
Write a 0 to this bit to clear it.
[3:2] I2CFIFOSTAT 0
Status bits for 3- or 4-bytes deep I
2
C FIFO. The FIFO monitored in these two bits is the one currently
used in I
2
C communication (receive or transmit) because only one FIFO is active at a time.
I2CFIFOSTAT Result
00 FIFO empty
01 Reserved
10 FIFO half full
11 FIFO full
1 I2CACC_ERR 0 Set when trying to write and read at the same time. Write a 0 to this bit to clear it.
0 I2CTxWR_ERR 0 Set when a write was attempted when the I
2
C transmit FIFO was full. Write a 0 to this bit to clear it.
READ AND WRITE OPERATIONS
SCLK
SDATA
START BY
MASTER
ACK BY
SLAVE
ACK BY
MASTER
FRAME 2
DATA BYTE 1 FROM MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
19 91
A0A1A2A3A4A5A6 R/W D0D1D2D3D4D5D6D7
91
D0D1D2D3D4D5D6D7
FRAME N + 1
DATA BYTE N FROM SLAVE
STOP BY
MASTER
NACK BY
MASTER
06353-087
Figure 113. I
2
C Read Operation
SCLK
SDATA
START BY
MASTER
ACK BY
SLAVE
ACK BY
SLAVE
FRAME 2
DATA BYTE 1 FROM MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
191 9
STOP BY
MASTER
A0A1A2A3A4A5A6 R/W D0D1D2D3D4D5D6D7
06353-088
Figure 114. I
2
C Write Operation
Figure 113 and Figure 114 depict I
2
C read and write operations,
respectively. Note that the LSB of the I2CADR SFR is used to
select whether a read or write operation is performed on the
slave device. During the read operation, the master acknowledges
are generated automatically by the I
2
C peripheral. The master
generated NACK (no acknowledge) before the end of a read
operation is also automatically generated after the I2CRCT bits
have been read from the slave. If the I2CADR register is
updated during a transmission, instead of generating a stop at
the end of the read or write operation, the master generates a
start condition and continues with the next communication.
Reading the SPI/I
2
C Receive Buffer SFR (SPI2CRx,
Address 0x9B)
Reading the SPI2CRx SFR should be done with a 2-cycle
instruction, such as
Mov a, spi2crx or Mov R0, spi2crx.
A 3-cycle instruction such as
Mov 3dh, spi2crx
does not transfer the right data into RAM Address 0x3D.