Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 14 of 152
Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters
Parameter Description Min Typ Max Unit
t
SS
SS to SCLK edge
145 ns
t
SL
SCLK low pulse width 6 × t
CORE
1
ns
t
SH
SCLK high pulse width 6 × t
CORE
1
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DSU
Data input setup time before SCLK edge 0 ns
t
DHD
Data input hold time after SCLK edge 2 × t
CORE
1
+ 0.5 μs μs
t
DF
Data output fall time 19 ns
t
DR
Data output rise time 19 ns
t
SR
SCLK rise time 19 ns
t
SF
SCLK fall time 19 ns
t
DOSS
Data output valid after SS
edge
0 ns
t
SFS
SS
high after SCLK edge
0 ns
1
t
CORE
depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t
CORE
= 2
CD
/4.096 MHz.
MSB
MOSI
BITS [6:1]
t
DHD
t
DSU
LSB IN
BITS [6:1]
LSB
t
DR
t
DF
t
DAV
MISO
t
SR
t
SF
t
SFS
t
SS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
t
SH
t
SL
t
DOSS
MSB IN
06353-007
Figure 8. SPI Slave Mode Timing (SPICPHA = 0)