Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 137 of 152
In both master and slave modes, the data is transmitted on one
edge of the SCLK signal and sampled on the other. It is important,
therefore, that the SPICPHA and SPICPOL bits be configured
the same for the master and slave devices.
SS
(Slave Select Pin)
In SPI slave mode, a transfer is initiated by the assertion of
SS
low. The SPI port then transmits and receives 8-bit data until
the data is concluded by the deassertion of
SS
according to the
SPICON bit setting. In slave mode,
SS
is always an input.
In SPI master mode, the
SS
(P0.7/T1) can be used to control
data transfer to a slave device. In the automatic slave select
control mode, the
SS
is asserted low to select the slave device
and then raised to deselect the slave device after the transfer is
complete. Automatic slave select control is enabled by setting the
AUTO_SS bit in the SPI Configuration SFR 1 (SPIMOD1,
Address 0xE8).
In a multimaster system, the
SS
can be configured as an input so
that the SPI peripheral can operate as a slave in some situations
and as a master in others. In this case, the slave selects for the
slaves controlled by this SPI peripheral should be generated
with general I/O pins.
SPI MASTER OPERATING MODES
The double buffered receive and transmit registers can be used to
maximize the throughput of the SPI peripheral by continuously
streaming out data in master mode. The continuous transmit mode
is designed to use the full capacity of the SPI. In this mode, the
master transmits and receives data until the SPI/I
2
C transmit
buffer SFR (SPI2CTx, Address 0x9A) is empty at the start of
a byte transfer. Continuous mode is enabled by setting the
SPICONT bit (Bit 7) in the SPI Configuration SFR 2 (SPIMOD2,
Address 0xE9). The SPI peripheral also offers a single byte
read/write function.
In master mode, the type of transfer is handled automatically,
depending on the configuration of the SPICONT bit in the SPI
Configuration SFR 2 (SPIMOD2, 0xE9). The following
procedures show the sequence of events that should be
performed for each master operating mode. Based on the
SS
configuration, some of these events take place automatically.
Procedures for Using SPI as a Master
Single Byte Write Mode, SPICONT (SPIMOD2[7]) = 0
1. Write to the SPI2CTx SFR.
2.
SS
is asserted low, and a write routine is initiated.
3. The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
4.
SS
is deasserted high.
5. Write to SPI2CTx SFR to clear the SPITxIRQ interrupt
flag.
6. Write to SPI2CTx SFR to clear the SPITxIRQ interrupt
flag.
Continuous Mode, SPICONT (SPIMOD2[7]) = 1
1. Write to the SPI2CTx SFR.
2.
SS
is asserted low, and a write routine is initiated.
3. Wait for the SPITxIRQ interrupt flag to write to SPI2CTx SFR.
4. Transfer continues until the SPI2CTx register and transmit
shift registers are empty.
5. The SPITxIRQ interrupt flag is set when the SPI2CTx
register is empty.
6.
SS
is deasserted high.
7. Write to SPI2CTx SFR to clear the SPITxIRQ interrupt flag.
Figure 110 shows the SPI output for certain automatic chip select
and continuous mode selections. Note that if the continuous mode
is not used, a short delay is inserted between transfers.
SCLK
SS
DOUT
DIN
DIN1 DIN2
AUTO_SS = 1
SPICONT = 0
SCLK
SS
DOUT
DIN
DIN1
AUTO_SS = 1
SPICONT = 1
DIN2
AUTO_SS = 0
SPICONT = 0
(MANUAL SS CONTROL)
DOUT1 DOUT2
DOUT1 DOUT2
SCLK
SS
DOUT
DIN
DIN1 DIN2
DOUT1 DOUT2
06353-084
Figure 110. Automatic Chip Select and Continuous Mode Output
Note that reading the content of the SPI/I
2
C receive buffer SFR
(SPI2CRx, Address 0x9B) should be done using a 2-cycle
instruction set such as MOV A or SPI2CRX. Using a 3-cycle
instruction such as MOV 0x3D or SPI2CRX does not transfer
the right information into the target register.