Datasheet
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 134 of 152
Table 148. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8)
Bit Address Mnemonic Default Description
[7:6]
0xEF to
0xEE
Reserved 0 Reserved.
5 0xED INTMOD 0 SPI interrupt mode.
INTMOD Result
0 SPI interrupt is set when the SPI Rx buffer is full.
1 SPI interrupt is set when the SPI Tx buffer is empty.
4 0xEC AUTO_SS 1
Master mode, SS
output control (see ). Figure 110
AUTO_SS Result
0
The SS
pin is held low while this bit is cleared. This allows manual chip select
control using the SS pin.
1
Single byte read or write. The SS
pin goes low during a single byte
transmission and then returns high.
Continuous Transfer. The SS
pin goes low during the duration of the multibyte
continuous transfer and then returns high.
3 0xEB SS_EN 0
Slave mode, SS
input enable.
When this bit is set to Logic 1, the SS
pin is defined as the slave select input pin for the SPI
slave interface.
2 0xEA RxOFW 0 Receive buffer overflow write enable.
RxOFW Result
0
If the SPI2CRx SFR has not been read when a new data byte is received,
the new byte is discarded.
1
If the SPI2CRx SFR has not been read when a new data byte is received,
the new byte overwrites the old data.
[1:0]
0xE9 to
0xE8
SPIR 0 Master mode, SPI SCLK frequency.
SPIR Result
00 f
CORE
/8 = 512 kHz (if f
CORE
= 4.096 MHz).
01 f
CORE
/16 = 256 kHz (if f
CORE
= 4.096 MHz).
10 f
CORE
/32 = 128 kHz (if f
CORE
= 4.096 MHz).
11 f
CORE
/64 = 64 kHz (if f
CORE
= 4.096 MHz).