Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 12 of 152
Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width 2
SPIR
× t
CORE
1
(SPIR + 1) × t
CORE
1
ns
t
SH
SCLK high pulse width 2
SPIR
× t
CORE
1
(SPIR + 1) × t
CORE
1
ns
t
DAV
Data output valid after SCLK edge 3 × t
CORE
1
ns
t
DOSU
Data output setup before SCLK edge 75 ns
t
DSU
Data input setup time before SCLK edge 0 ns
t
DHD
Data input hold time after SCLK edge t
CORE
1
ns
t
DF
Data output fall time 19 ns
t
DR
Data output rise time 19 ns
t
SR
SCLK rise time 19 ns
t
SF
SCLK fall time 19 ns
1
t
CORE
depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t
CORE
= 2
CD
/4.096 MHz.
SCLK
(SPICPOL = 0)
t
DSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB
LSB
LSB IN
BITS [6:1]
BITS [6:1]
t
DHD
t
DR
t
DAV
t
DF
t
DOSU
t
SH
t
SL
t
SR
t
SF
MSB IN
0
6353-005
Figure 6. SPI Master Mode Timing (SPICPHA = 0)