Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 115 of 152
TIMERS
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 has three 16-bit timer/counters: Timer/Counter 0,
Timer/Counter 1, and Timer/Counter 2. The timer/counter
hardware is included on-chip to relieve the processor core of
overhead inherent in implementing timer/counter functionality
in software. Each timer/counter consists of two 8-bit registers:
THx and TLx (x = 0, 1, or 2). All three timers can be configured
to operate as timers or as event counters.
When functioning as a timer, the TLx SFR is incremented every
machine cycle. (Users can think of it as counting machine cycles.)
Because a machine cycle on a single-cycle core consists of one core
clock period, the maximum count rate is the core clock frequency.
When functioning as a counter, the TLx register is incremented
by a 1-to-0 transition at its corresponding external input pin:
T0, T1, or T2. When the samples show a high in one cycle and a
low in the next cycle, the count is incremented. Because it takes
two machine cycles (two core clock periods) to recognize a 1-to-0
transition, the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via the SFRs listed in Table 112.
Table 112. Timer SFRs
SFR Address Bit Addressable Description
TCON 0x88 Yes Timer/Counter 0 and Timer/Counter 1 control (see Table 114).
TMOD 0x89 No Timer/Counter 0 and Timer./Counter 1 mode (see Table 113).
TL0 0x8A No Timer 0 low byte (see Table 117).
TL1 0x8B No Timer 1 low byte (see Table 119).
TH0 0x8C No Timer 0 high byte (see Table 116).
TH1 0x8D No Timer 1 high byte (see Table 118).
T2CON 0xC8 Yes Timer/Counter 2 control (see Table 115).
RCAP2L 0xCA No Timer 2 reload/capture low byte (see Table 123).
RCAP2H 0xCB No Timer 2 reload/capture high byte (see Table 122).
TL2 0xCC No Timer 2 low byte (Table 121).
TH2 0xCD No Timer 2 high byte (see Table 120).
TIMER REGISTERS
Table 113. Timer/Counter 0 and Timer/Counter 1 Mode SFR (TMOD, Address 0x89)
Bit Mnemonic Default Description
7 Gate1 0
Timer 1 gating control. Set by software to enable Timer/Counter 1 only when the INT1
pin is high and the
TR1 control is set. Cleared by software to enable Timer 1 whenever the TR1 control bit is set.
6
C/T1
0
Timer 1 timer or counter select bit. Set by software to select counter operation (input from T1 pin). Cleared
by software to select the timer operation (input from internal system clock).
[5:4]
T1/M1,
T1/M0
00 Timer 1 mode select bits.
T1/M1, T1/M0 Result
00
TH1 (Address 0x8D) operates as an 8-bit timer/counter. TL1 (Address 0x8D) serves as
5-bit prescaler.
01 16-bit timer/counter. TH1 and TL1 are cascaded; there is no prescaler.
10 8-bit autoreload timer/counter. TH1 holds a value to reload into TL1 each time it overflows.
11 Timer/Counter 1 stopped.
3 Gate0 0
Timer 0 gating control. Set by software to enable Timer/Counter 0 only when the INT0
pin is high and the TR0
control bit is set. Cleared by software to enable Timer 0 whenever the TR0 control bit is set in the
Timer/Counter 0 and Timer/Counter 1 control SFR (TCON, Address 0x88)
2
C/T0
0
Timer 0 timer or counter select bit. Set by software to the select counter operation (input from T0 pin).
Cleared by software to the select timer operation (input from internal system clock).
[1:0]
T0/M1,
T0/M0
00 Timer 0 mode select bits.
T0/M1, T0/M0 Result
00 TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
01 16-bit timer/counter. TH0 and TL0 are cascaded; there is no prescaler.
10 8-bit autoreload timer/counter. TH0 holds a value to reload into TL0 each time it overflows.
11
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an
8-bit timer only, controlled by Timer 1 control bits.