Datasheet

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Rev. B | Page 10 of 152
TIMING SPECIFICATIONS
AC inputs during testing were driven at V
SWOUT
− 0.5 V for Logic 1
and at 0.45 V for Logic 0. Timing measurements were made at V
IH
minimum for Logic 1 and at V
IL
maximum for Logic 0, as shown in
Figure 3.
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded V
OH
/V
OL
level
occurs, as shown in Figure 3.
C
LOAD
for all outputs is equal to 80 pF, unless otherwise noted.
V
DD
= 2.7 V to 3.6 V; all specifications T
MIN
to T
MAX
, unless
otherwise noted.
V
SWOUT
– 0.5V
0.45V
0.2V
SWOUT
+ 0.9V
TEST POINTS
0.2V
SWOUT
– 0.1V
V
LOAD
– 0.1V
V
LOAD
V
LOAD
+ 0.1V
TIMING
REFERENCE
POINTS
V
LOAD
– 0.1V
V
LOAD
V
LOAD
– 0.1V
06353-002
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameter
32.768 kHz External Crystal
Parameter Description Min Typ Max Unit
t
CK
XTAL1 period 30.52 μs
t
CKL
XTAL1 width low 6.26 μs
t
CKH
XTAL1 width high 6.26 μs
t
CKR
XTAL1 rise time 9 ns
t
CKF
XTAL1 fall time 9 ns
1/t
CORE
Core clock frequency
1
1.024 MHz
1
The internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can
operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I
2
C-Compatible Interface Timing Parameters (400 kHz)
Parameter Description Typ Unit
t
BUF
Bus-free time between stop condition and start condition 1.3 μs
t
L
SCLK low pulse width 1.36 μs
t
H
SCLK high pulse width 1.14 μs
t
SHD
Start condition hold time 251.35 μs
t
DSU
Data setup time 740 ns
t
DHD
Data hold time 400 ns
t
RSU
Setup time for repeated start 12.5 ns
t
PSU
Stop condition setup time 400 ns
t
R
Rise time of both SCLK and SDATA 200 ns
t
F
Fall time of both SCLK and SDATA 300 ns
t
SUP
1
Pulse width of spike suppressed 50 ns
1
Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of <50 ns.
MSB
t
BUF
SDATA (I/O)
SCLK (I)
STOP
CONDITION
START
CONDITION
REPEATED
START
LSB ACK MSB
1
2TO 7
89 1
S(R)
PS
t
PSU
t
DSU
t
SHD
t
DHD
t
SUP
t
DSU
t
DHD
t
H
t
SUP
t
L
t
RSU
t
R
t
R
t
F
t
F
06353-003
Figure 4. I
2
C-Compatible Interface Timing