Single-Phase Energy Measurement IC with 8052 MCU, RTC, and LCD Driver ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 GENERAL FEATURES MICROPROCESSOR FEATURES Wide supply voltage operation: 2.4 V to 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power saving modes (PSM) Full operation: 4 mA to 1.6 mA (PLL clock dependent) Battery mode: 3.2 mA to 400 μA (PLL clock dependent) Sleep mode Real-time clock (RTC) mode: 1.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TABLE OF CONTENTS General Features ............................................................................... 1 Fault Detection ........................................................................... 54 Energy Measurement Features........................................................ 1 Microprocessor Features.................................................................. 1 di/dt Current Sensor and Digital Integrator for the ADE7169/ADE7569 ...
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 LCD Driver ................................................................................... 100 RTC Calibration ........................................................................125 LCD Registers ........................................................................... 100 UART Serial Interface ...................................................................126 LCD Setup ........................................................................
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 GENERAL DESCRIPTION The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 1 integrate the Analog Devices, Inc., energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, an RTC, an LCD driver, and all the peripherals to make an electronic energy meter with an LCD display in a single part.
TEMP ADC BATTERY ADC P1.4/T2/FP23 P1.5/FP22 P1.2/FP25 P1.3/T2EX/FP24 P1.6/FP21 P1.7/FP20 P2.0/FP18 13 P2.1/FP17 14 P2.2/FP16 44 19 P2.3 (SDEN/P2.3) LCDVP1 16 LCDVP2 18 LCDVA 17 LCDVB 15 LCDVC 4 COM0 1 35 ... COM3 FP0 ...
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 SPECIFICATIONS VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted. ENERGY METERING Table 2. Parameter MEASUREMENT ACCURACY 1 Phase Error Between Channels2 PF = 0.8 Capacitive PF = 0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ANALOG PERIPHERALS Table 3. Parameter INTERNAL ADCs (BATTERY, TEMPERATURE, VDCIN) 1 Power Supply Operating Range No Missing Codes 2 Conversion Delay 3 ADC Gain VDCIN Measurement VBAT Measurement Temperature Measurement ADC Offset VDCIN Measurement at 3 V VBAT Measurement at 3.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Parameter LCD, RESISTOR LADDER ACTIVE Leakage Current V1 Segment Line Voltage V2 Segment Line Voltage V3 Segment Line Voltage ON-CHIP REFERENCE Reference Error Power Supply Rejection Temperature Coefficient2 Min Typ Max Unit Test Conditions/Comments LCDVA LCDVB LCDVC nA V V V 1/2 and 1/3 bias modes, no load Current on segment line = −2 μA Current on segment line = −2 μA Current on segment line = −2 μA mV dB ppm/°C TA = 25°C ±20 LCDVA − 0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Parameter POWER SUPPLY INPUTS VDD VBAT INTERNAL POWER SUPPLY SWITCH (VSWOUT) VBAT to VSWOUT On Resistance VDD to VSWOUT On Resistance VBAT to/from VDD Switching Open Time BCTRL State Change and Switch Delay VSWOUT Output Current Drive POWER SUPPLY OUTPUTS VINTA VINTD VINTA Power Supply Rejection VINTD Power Supply Rejection POWER SUPPLY CURRENTS Current in Normal Mode (PSM0) Current in PSM1 Current in PSM2 Min Typ Max Unit 3.13 2.4 3.3 3.3 3.46 3.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TIMING SPECIFICATIONS float when a 100 mV change from the loaded VOH/VOL level occurs, as shown in Figure 3. AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1 and at 0.45 V for Logic 0. Timing measurements were made at VIH minimum for Logic 1 and at VIL maximum for Logic 0, as shown in Figure 3. CLOAD for all outputs is equal to 80 pF, unless otherwise noted. VDD = 2.7 V to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF Min 2SPIR × tCORE 1 2SPIR × tCORE1 Typ Max 3 × tCORE1 0 tCORE1 19 19 19 19 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz. SCLK (SPICPOL = 0) tSH tSL tSR SCLK (SPICPOL = 1) tDAV tDF tSF tDR MOSI MSB MSB IN MISO tDSU BITS [6:1] BITS [6:1] tDHD Figure 5.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF Min 2SPIR × tCORE 1 2SPIR × tCORE1 Typ (SPIR + 1) × tCORE1 (SPIR + 1) × tCORE1 Max 3 × tCORE1 75 0 tCORE1 19 19 19 19 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter tSS Description SS to SCLK edge Min 145 tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time SS high after SCLK edge 6 × tCORE 1 6 × tCORE1 Max 25 0 2 × tCORE1 + 0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 10.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 11. Parameter VDD to DGND VBAT to DGND VDCIN to DGND Input LCD Voltage to AGND, LCDVA, LCDVB, LCDVC1 Analog Input Voltage to AGND, VP, VN, IP, IPA, IPB, and IN Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range (Industrial) Storage Temperature Range 64-Lead LQFP, Power Dissipation Lead Temperature (Soldering, 30 sec) 1 Rating −0.3 V to +3.7 V −0.3 V to +3.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDCIN DGND VINTD VSWOUT VDD VINTA VBAT REFIN/OUT RESET FP26 AGND IN IP EA VN VP PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR ADE7566/ADE7569 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 INT0 XTAL1 XTAL2 BCTRL/INT1/P0.0 SDEN/P2.3 P0.2/CF1/RTCCAL P0.3/CF2 P0.4/MOSI/SDATA P0.5/MISO P0.6/SCLK/T0 P0.7/SS/T1 P1.0/RxD P1.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Pin No. 18 Mnemonic LCDVA 19 LCDVP1 20 to 35 36 37 38 39 40 41 42 FP15 to FP0 P1.1/TxD P1.0/RxD P0.7/SS/T1 P0.6/SCLK/T0 P0.5/MISO P0.4/MOSI/SDATA P0.3/CF2 43 P0.2/CF1/RTCCAL 44 SDEN/P2.3 45 BCTRL/INT1/P0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Pin No. 60 Mnemonic VDD 61 VSWOUT 62 VINTD 63 64 DGND VDCIN EP Exposed Pad Description 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 3.3 V Power Supply Output.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDCIN DGND VINTD VSWOUT VDD VINTA VBAT REFIN/OUT RESET IPB AGND IN IPA EA VN VP ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR ADE7116/ADE7156/ ADE7166/ADE7169 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 INT0 XTAL1 XTAL2 BCTRL/INT1/P0.0 SDEN/P2.3 P0.2/CF1/RTCCAL P0.3/CF2 P0.4/MOSI/SDATA P0.5/MISO P0.6/SCLK/T0 P0.7/SS/T1 P1.0/RxD P1.1/TxD FP0 FP1 FP2 NOTES 1.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Pin No. 18 Mnemonic LCDVA 19 LCDVP1 20 to 35 36 37 38 39 40 41 42 FP15 to FP0 P1.1/TxD P1.0/RxD P0.7/SS/T1 P0.6/SCLK/T0 P0.5/MISO P0.4/MOSI/SDATA P0.3/CF2 43 P0.2/CF1/RTCCAL 44 SDEN/P2.3 45 BCTRL/INT1/P0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Pin No. 59 Mnemonic VINTA 60 VDD 61 VSWOUT 62 VINTD 63 64 DGND VDCIN EP Exposed Pad Description This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 3.3 V Power Supply Input from the Regulator.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 2.0 MID CLASS C GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE 1.5 0.5 1.0 ERROR (% of Reading) ERROR (% of Reading) 1.0 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE +85°C; PF = 1 +25°C; PF = 1 0 –40°C; PF = 1 –0.5 –1.0 –1.5 +85°C; PF = 0.866 +25°C; PF = 0.866 –40°C; PF = 0.866 0.5 0 +85°C; PF = 0 +25°C; PF = 0 –40°C; PF = 0 –0.5 –1.0 –1.5 1 10 100 CURRENT CHANNEL (% of Full Scale) Figure 11.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 0.5 0.4 1.5 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE 1.0 0.2 Irms; 3.3V 0.1 Vrms; 3.3V Irms; 3.43V ERROR (% of Reading) ERROR (% of Reading) 0.3 Vrms; 3.43V Vrms; 3.13V 0 –0.1 Irms; 3.13V –0.2 –0.3 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE MID CLASS C 0.5 PF = 1 PF = –0.5 0 PF = +0.5 –0.5 MID CLASS C –1.0 10 100 CURRENT CHANNEL (% of Full Scale) –1.5 0.1 Figure 17.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 1.0 2.0 1.5 GAIN = 16 INTEGRATOR OFF INTERNAL REFERENCE GAIN = 16 0.8 INTEGRATOR OFF INTERNAL REFERENCE MID CLASS C 0.6 –40°C; PF = 0 +85°C; PF = 0 +85°C; PF = 0.866 –40°C; PF = 0.866 0.5 ERROR (% of Reading) ERROR (% of Reading) 1.0 +25°C; PF = 1 0 –40°C; PF = 1 –0.5 +85°C; PF = 1 –1.0 0.4 0.2 0 +25°C; PF = 0.866 +25°C; PF = 0 –0.2 –0.4 –0.6 –1.5 10 100 CURRENT CHANNEL (% of Full Scale) –1.0 0.1 06353-097 1 Figure 23.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY 2.0 0.5 1.5 –40°C; PF = 1 +85°C; PF = 0.5 +25°C; PF = 0.5 –40°C; PF = 0.5 1.0 0 –0.5 GAIN = 16 INTEGRATOR ON INTERNAL REFERENCE +25°C; PF = 1 +85°C; PF = 1 –1.0 –1.5 0.5 +25°C; PF = 1 +25°C; PF = 0.5 +85°C; PF = 0.5 +85°C; PF = 1 –40°C; PF = 0.5 0 –0.5 –40°C; PF = 1 –1.0 –1.5 MID CLASS C 1 10 MID CLASS C 100 CURRENT CHANNEL (% of Full Scale) –2.0 0.1 06353-103 –2.0 0.1 Figure 29.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is defined by the following formula: For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 SPECIAL FUNCTION REGISTER (SFR) MAPPING Table 15.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Mnemonic HTHSEC Address 0xA2 TIMECON P2 EPCFG 0xA1 0xA0 0x9F SBAUDT 0x9E SBAUDF 0x9D LCDCONX SPI2CRx SPI2CTx SBUF SCON 0x9C 0x9B 0x9A 0x99 0x98 LCDSEGE LCDCLK LCDCON MDATH 0x97 0x96 0x95 0x94 Description RTC hundredths of a second counter (see Table 129). RTC configuration (see Table 128). Port 2 (see Table 162). Extended port configuration (see Table 156). Enhanced serial baud rate control (see Table 142).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 POWER MANAGEMENT The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have elaborate power management circuitry that manages the switchover from regular power supply to battery and manages power supply failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Table 16). Table 16.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8) Bit 7 Bit Address 0xFF Mnemonic FPSR Default 0 6 5 4 3 0xFE 0xFD 0xFC 0xFB FPSM FSAG Reserved FVADC 1 0 0 0 0 2 1 0 0xFA 0xF9 0xF8 FBAT1 FBSO FVDCIN1 0 0 0 1 Description Power supply restored interrupt flag. Set when the VDD power supply has been restored. This occurs when the source of VSWOUT changes from VBAT to VDD. PSM interrupt flag.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB) Bit [7:0] Mnemonic SCRATCH1 Default 0 Description Value can be written/read in this register. This value is maintained in all the power saving modes. Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC) Bit [7:0] Mnemonic SCRATCH2 Default 0 Description Value can be written/read in this register. This value is maintained in all the power saving modes. Table 24.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 POWER SUPPLY ARCHITECTURE Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has two power supply inputs, VDD and VBAT, which require only a single 3.3 V power supply at VDD for full operation. A battery backup, or secondary power supply, with a maximum of 3.7 V can be connected to the VBAT input. Internally, the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 connect VDD or VBAT to VSWOUT, which is used to derive power for the device circuitry.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The power management interrupt enable SFR (IPSME, Address 0xEC) controls the events that result in a PSM interrupt (see Table 21). Figure 33 illustrates how the PSM interrupt vector is shared among the PSM interrupt sources. The PSM interrupt flags are latched and must be cleared by writing to the IPSMF power management interrupt flag SFR, Address 0xF8 (see Table 18).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Battery Switchover and Power Supply Restored PSM Interrupt VBAT Monitor PSM Interrupt The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can be configured to generate a PSM interrupt when the source of VSWOUT changes from VDD to VBAT, indicating battery switchover. Setting the EBSO bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt (see Table 21).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 USING THE POWER SUPPLY FEATURES In an energy meter application, the 3.3 V power supply (VDD) is typically generated from the ac line voltage and regulated to 3.3 V by a voltage regulator IC. The preregulated dc voltage, typically 5 V to 12 V, can be connected to VDCIN through a resistor divider. A 3.6 V battery can be connected to VBAT. Figure 34 shows how the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 power supply inputs are set up in this application.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 27. Power Supply Event Timing Operating Modes Parameter t1 t2 t3 Time 10 ns min 10 ns min 30 ms typ t4 130 ms typ Description Time between when VDCIN goes below 1.2 V and when FVDCIN is raised. Time between when VDD falls below 2.75 V and when battery switchover occurs. Time between when VDCIN falls below 1.2 V and when battery switchover occurs if VDCIN is enabled to cause battery switchover.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 OPERATING MODES • PSM0 (NORMAL MODE) In PSM0, or normal operating mode, VSWOUT is connected to VDD. All of the analog circuitry and the digital circuitry powered by VINTD and VINTA are enabled by default. In normal mode, the default clock frequency, fCORE, which is established during a power-on reset or software reset, is 1.024 MHz. PSM1 (BATTERY MODE) In PSM1, or battery mode, VSWOUT is connected to VBAT.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 3.3 V PERIPHERALS AND WAKE-UP EVENTS Some of the 3.3 V peripherals are capable of waking the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2 mode. The events that can cause the devices to wake up from PSM2 mode are listed in the Wake-Up Event column in Table 29. The interrupt flag associated with these events must be cleared prior to executing instructions that put the ADE7116/ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 in PSM2 mode after wake-up.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TRANSITIONING BETWEEN OPERATING MODES Automatic Switch to VDD (PSM2 to PSM0) The operating mode of the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 is determined by the power supply connected to VSWOUT. Therefore, changes in the power supply, such as when VSWOUT switches from VDD to VBAT or when VSWOUT switches to VDD, alter the operating mode. This section describes events that change the operating mode.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ENERGY MEASUREMENT The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 offer a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through SFRs for time sensitive information and indirect access through address and data SFRs for the majority of energy measurements.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 31. Energy Measurement SFRs Address 0x91 0x92 0x93 0x94 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 R/W R/W R/W R/W R/W R R R R R R R/W R/W R/W R/W R/W R/W R R R R R R IP ×1, ×2, ×4, ×8, ×16 {GAIN[2:0]} Description Energy measurement pointer address. Energy measurement pointer data LSB. Energy measurement pointer data middle byte. Energy measurement pointer data MSB. Vrms measurement LSB.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 INTEGRATOR PGA1 I ADC WGAIN[11:0] MULTIPLIER HPF IN dt PGA1 ADC LPF2 HPF IPB WATTOS[15:0] π 2 IBGAIN[11:0] CF1NUM[15:0] VARGAIN[11:0] PHCAL[7:0] CF1 DFC Ф LPF2 CF1DEN[15:0] IRMSOS[11:0] VAROS[15:0] CF2NUM[15:0] VAGAIN[11:0] ×2 VARDIV[7:0] V2P PGA2 V2N ADC HPF ×2 CF2 DFC LPF VRMSOS[11:0] CF2DEN[15:0] LPF VADIV[7:0] % % % METERING SFRs Figure 40. ADE7116, ADE7156, ADE7166, and ADE7169 Energy Metering Block Diagram Rev.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ENERGY MEASUREMENT REGISTERS Table 32.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Address MADDPT[6:0] 0x25 0x26 0x27 0x28 0x29 0x2A 0x3B 0x3C 0x3D 0x3E 0x3F 1 2 Mnemonic VARDIV VADIV CF1NUM CF1DEN CF2NUM CF2DEN Reserved Reserved CALMODE2 Reserved Reserved R/W R/W R/W R/W R/W R/W R/W Length (Bits) 8 8 16 16 16 16 Signed/ Unsigned U U U U U U R/W 8 U Default 0 0 0 0x003F 0 0x003F 0 0x0300 0 0 0 Description Sets var energy scaling register. Sets VA energy scaling register. Sets CF1 numerator register. Sets CF1 denominator register.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Bit 1 Mnemonic FREQSEL Default 0 0 WAVEN 0 1 Description Configuration bits to select period or frequency measurement for PER_FREQ register (Address 0x0A). FREQSEL Result 0 PER_FREQ register holds a period measurement. 1 PER_FREQ register holds a frequency measurement. When this bit is set, waveform sampling mode is enabled. This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566. Table 35.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Bit [3:2] Mnemonic VARNOLOAD1 Default 00 [1:0] APNOLOAD 00 1 Description Reactive power no load threshold. VARNOLOAD Result 00 No load detection disabled 01 No load detection enabled with threshold = 0.015% of full scale 10 No load detection enabled with threshold = 0.0075% of full scale 11 No load detection enabled with threshold = 0.0037% of full scale Active power no load threshold.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Bit 3 Mnemonic CFSIGN_OPT Default 0 [2:0] PGA1 000 1 Description This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented. CFSIGN_OPT Result 0 Filtered power signal 1 On a per-CF basis These bits define the current channel input gain.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 41. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD) Bit 7 Interrupt Flag CF2 6 CF1 5 4 3 2 1 0 VAEOF REOF 1 AEOF VAEHF REHF1 AEHF 1 Description Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not enabled by clearing Bit 2 of the MODE1 register. Logic 1 indicates that a pulse on CF1 has been issued.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 45. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) Bit [7:6] 5 4 3 2 1 0 Interrupt Enable Bit Reserved WFSM PKI PKV CYCEND ZXTO ZX Description Reserved. When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core. When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core. When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ANALOG-TO-DIGITAL CONVERSION ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is 4.096 MHz/5 (819.2 kHz), and the band of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered (see Figure 43).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ALIASING EFFECTS Figure 44 also shows an analog LPF (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC that are higher than half the sampling rate of the ADC appear in the sampled signal at a frequency below half the sampling rate. Figure 45 illustrates the effect.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ×1, ×2, ×4 ×8, ×16 {GAIN[2:0]} MODE1[5] PGA1 WAVEFORM SAMPLE REGISTER DIGITAL INTEGRATOR* IP I CURRENT RMS (I rms) CALCULATION REFERENCE ADC IN ACTIVE AND REACTIVE POWER CALCULATION dt HPF CURRENT CHANNEL WAVEFORM DATA RANGE AFTER INTEGRATOR (50Hz) 50Hz V1 0.25V, 0.125V, 62.5mV, 31.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Voltage Channel ADC Figure 48 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces an output code that is approximately between 0x28F5 (+10,485d) and 0xD70B (−10,485d).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 FAULT DETECTION Fault Indication The ADE7116/ADE7156/ADE7166/ADE7169 incorporate a fault detection scheme that warns of fault conditions and allows the part to continue accurate measurement during a fault event. (This function is not available in the ADE7566/ ADE7569.) The ADE7116/ADE7156/ADE7166/ADE7169 do this by continuously monitoring both current inputs (IPA and IPB).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Fault with Inactive Input Greater Than Active Input IPB Typically, when a meter is calibrated, the voltage and current circuits are separated, as shown in Figure 49. Current passes through only the phase circuit or the neutral circuit. Figure 49 shows current being passed through the phase circuit. This is the preferred option because the ADE7116/ADE7156/ ADE7166/ADE7169 start billing on the IPA input on power-up.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 10 –1.0 –1.5 –2.0 –2.5 GAIN (dB) The ADE7169/ADE7569 have a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on the current channel is switched off by default when the ADE7169/ADE7569 are powered up. Setting the INTE bit (Bit 5) in the MODE1 register (Address 0x0B) turns on the integrator. Figure 51 to Figure 54 show the gain and phase response of the digital integrator. –3.0 –3.5 –4.0 –4.5 0 –5.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 POWER QUALITY MEASUREMENTS Zero-Crossing Detection Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has a zero-crossing detection circuit on the voltage channel. This zero crossing is used to produce a zero-crossing internal signal (ZX) and is used in calibration mode. The zero crossing is generated by default from the output of LPF1. This filter has a low cutoff frequency and is intended for 50 Hz and 60 Hz systems.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 V2 Line Voltage SAG Detection In addition to detection of the loss of the line voltage signal (zero crossing), the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illustrated in Figure 57.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 PHASE COMPENSATION RMS CALCULATION The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The update rate of the current channel rms measurement is 4.096 MHz/5. To minimize noise in the reading of the register, the Irms register can also be configured to update only with the zero crossing of the voltage input. This configuration is done by setting the ZXRMS bit (Bit 2) in the MODE2 register (Address 0x0C).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 60Hz CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR ON (60Hz) 0x2B7850 0x000000 0xD487B0 IRMSOS[11:0] MODE1[5] IPA IPB sgn 225 226 227 HPF DIGITAL INTEGRATOR* Irms(t) 218 217 216 0x00 HPF1 LPF3 24 + 24 Irms[23:0] dt HPF CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR OFF IBGAIN 0x28F5C2 0x000000 06353-116 0xD70A3E *NOT AVAILABLE IN THE ADE7116, ADE7156, OR ADE7166. Figure 62.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Figure 63 shows details of the signal processing chain for the rms calculation on the voltage channel. This voltage rms estimation is done in the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 using the mean absolute value calculation, as shown in Figure 63. The voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode and is stored in the unsigned 24-bit Vrms register.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 0 register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on the voltage and current channels are both at full scale. At −60 dB down on the current channel (1/1000 of the current channel full-scale input), the average word value output from LPF2 is 838.861 (838,861/1000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 power signal in the waveform register is continuously added to the internal active energy register. ACTIVE ENERGY CALCULATION As stated in the Active Power Calculation section, power is defined as the rate of energy flow. This relationship can be expressed mathematically, as shown in Equation 13. P= dE dt (13) The active energy accumulation depends on the setting of POAM (Bit 1) and ABSAM (Bit 0) in the ACCMODE register (Address 0x0F).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Figure 67 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 0x7FF, 0x000, and 0x800. The watt gain register is used to carry out power calibration in the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ADE7566/ADE7569 can be synchronized to the voltage channel zero crossing so that active energy can be accumulated over an integral number of half-line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 When a new half-line cycle is written in the LINCYC register (Address 0x12), the LWATTHR register (Address 0x03) is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register (see Figure 71).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Reactive Power Gain Calibration Figure 72 shows the signal processing chain for the ADE7169/ ADE7569 reactive power calculation. As explained in the Reactive Power Calculation (ADE7169/ADE7569) section, the reactive power is calculated by applying a low-pass filter to the instantaneous reactive power signal.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The reactive energy accumulation depends on the setting of the SAVARM and ABSVARM bits in the ACCMODE register (Address 0x0F). When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the reactive energy contents. When both bits are set, the ADE7169/ADE7569 are set to be in the more restrictive mode, which is the absolute accumulation mode.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Integration Time Under Steady Load: Reactive Energy As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is 1.22 μs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the VARGAIN register (Address 0x1E) and the VARDIV register (Address 0x25) set to 0x000, the integration time before the reactive energy register overflows is calculated in Equation 26.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Var Absolute Accumulation Mode Line Cycle Reactive Energy Accumulation Mode The ADE7169/ADE7569 are placed in absolute accumulation mode by setting the ABSVARM bit (Bit 3) in the ACCMODE register (Address 0x0F). In absolute accumulation mode, the reactive energy accumulation is done by using the absolute reactive power and ignoring any occurrence of power below the no load threshold for the reactive energy (see Figure 74).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 APPARENT POWER CALCULATION Apparent power is defined as the maximum power that can be delivered to a load. Vrms and Irms are the effective voltage and current delivered to the load, respectively. Therefore, the apparent power (AP) = Vrms × Irms. This equation is independent of the phase angle between the current and the voltage.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 provided to read the apparent energy. This register is reset to 0 after a read operation. APPARENT ENERGY CALCULATION The apparent energy is given as the integral of the apparent power. Apparent Energy = ∫ Apparent Power(t )dt Note that the apparent energy register is unsigned.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Apparent Energy Pulse Output All the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 circuitry has a pulse output whose frequency is proportional to apparent power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VAGAIN. This output can also be used to output a pulse whose frequency is proportional to Irms.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 APPARENT POWER or Irms + % + 48 0 LVAHR REGISTER IS UPDATED EVERY LINCYC ZERO CROSSING WITH THE TOTAL APPARENT ENERGY DURING THAT DURATION VADIV[7:0] 23 LPF1 CALIBRATION CONTROL ZERO-CROSSING DETECTION 0 LVAHR[23:0] 06353-053 FROM VOLTAGE CHANNEL ADC LINCYC[15:0] Figure 78.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 If 0 is written to any of these registers, 1 is applied to the register. The ratio of CFxNUM/CFxDEN should be less than 1 to ensure proper operation. If the ratio of the CFxNUM/CFxDEN registers is greater than 1, the register values are adjusted to a ratio of 1. For example, if the output frequency is 1.562 kHz, and the content of CFxDEN is 0 (0x000), the output frequency can be set to 6.1 Hz by writing 0xFF to the CFxDEN register.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 include temperature measurements as well as battery and supply voltage measurements. (This feature is not available in the ADE7116.) These measurements enable many forms of compensation. The temperature and supply voltage measurements can be used to compensate external circuitry. The RTC can be calibrated over temperature to ensure that it does not drift.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 50. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3) Bit [7:6] [5:3] Mnemonic Reserved TEMP_DIFF Default 0 0 [2:0] VDCIN_DIFF 0 Description Reserved. Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052. TEMP_DIFF Result 000 No interrupt 001 1 LSB (≈ 0.8°C) 010 2 LSB (≈ 1.6°C) 011 3 LSB (≈ 2.4°C) 100 4 LSB (≈ 3.2°C) 101 5 LSB (≈ 4°C) 110 6 LSB (≈ 4.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TEMPERATURE MEASUREMENT • To provide a digital temperature measurement, each ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 includes a dedicated ADC. An 8-bit temperature ADC value SFR (TEMPADC, Address 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78°C/LSB. There are two ways to initiate a temperature conversion: a single temperature measurement or background temperature measurements.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 This low battery flag can be enabled to generate the PSM interrupt by setting the EBAT bit (Bit 2) in the power management interrupt enable SFR (IPSME, Address 0xEC). This method allows battery measurements to take place completely in the background, requiring MCU activity only if the battery drops below a user-specified threshold. To set up background battery measurements, follow these steps: 1. 2.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 External Voltage ADC in PSM0, PSM1, and PSM2 Modes An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569. • • • In PSM0 operating mode, the 8052 is active. External voltage measurements are available in the background measurement mode and by initiating a single measurement. In PSM1 operating mode, the 8052 is active and the part is powered from battery.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 8052 MCU CORE ARCHITECTURE The special function register (SFR) space is mapped into the upper 128 bytes of internal data memory space and is accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. See Figure 81 for a block diagram of the programming model for the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 via the SFR area.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 58. Program Control SFR (PCON, Address 0x87) Bit 7 [6:0] Mnemonic SMOD Reserved Default 0 0 Description Double baud rate control. Reserved. These bits must be kept at 0 for proper operation. Table 59. Data Pointer Low SFR (DPL, Address 0x82) Bit [7:0] Mnemonic DPL Default 0 Description These bits contain the low byte of the data pointer. Table 60.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 BASIC 8052 REGISTERS Program Counter (PC) Data Pointer (DPTR) The program counter holds the 2-byte address of the next instruction to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that the amount that is added to the PC depends on the number of bytes in the instruction, therefore, the increment can range from one to three bytes.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 STANDARD 8052 SFRs Power Control Register (PCON, Address 0x87) The standard 8052 SFRs include the accumulator (ACC), B, PSW, DPTR, and SP SFRs, as described in the Basic 8052 Registers section. The 8052 also defines standard timers, serial port interfaces, interrupts, I/O ports, and power-down modes. The 8052 core defines two power-down modes: power-down and idle.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Address 0x80 through Address 0xFF of general-purpose RAM are shared with the SFRs. The mode of addressing determines which memory space is accessed, as shown in Figure 84. 0xFF ACCESSIBLE BY DIRECT ADDRESSING ONLY The individual bits of some of the SFRs can be accessed for use in Boolean and program branching instructions. These SFRs are labeled as bit-addressable and the bit addresses are given in Table 15.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Immediate Addressing In immediate addressing, the expression entered after the number sign (#) is evaluated by the assembler and stored in the memory address specified. This number is referred to as a literal because it refers only to a value and not to a memory location. Instructions using this addressing mode are slower than those between two registers because the literal must be stored and fetched from memory.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 INSTRUCTION SET Table 65 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 4-MIPS peak performance. Note that throughout this section, A represents the accumulator. Table 65.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Mnemonic RLC A RR A RRC A Data Transfer MOV A,Rn MOV A,@Ri MOV Rn,A MOV @Ri,A MOV A,dir MOV A,#data MOV Rn,#data MOV dir,A MOV Rn,dir MOV dir,Rn MOV @Ri,#data MOV dir,@Ri MOV @Ri,dir MOV dir,dir MOV dir,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,@Ri XCHD A,@Ri XCH A,dir Boolean CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit OR MOV C,bit
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Mnemonic JNC rel JZ rel JNZ rel DJNZ Rn,rel LJMP LCALL addr16 JB bit,rel JNB bit,rel JBC bit,rel CJNE A,dir,rel CJNE A,#data,rel CJNE Rn,#data,rel CJNE @Ri,#data,rel DJNZ dir,rel MISCELLANEOUS NOP Description Jump on carry equal to 0 Jump on accumulator = 0 Jump on accumulator ≠ 0 Decrement register, JNZ relative Long jump unconditional Long jump to subroutine Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Compare A, direct JNE
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 SUBB A, Source to correct the lower four bits. If the carry bit is set when the instruction begins, or if 0x06 is added to the accumulator in the first step, 0x60 is added to the accumulator to correct the higher four bits. This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag. The carry and AC status flags are referenced by this instruction. Table 69.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 DUAL DATA POINTERS Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON, Address 0xA7). DPCON features automatic hardware postincrement and postdecrement, as well as an automatic data pointer toggle. Note that this is the only section of the data sheet where the main and shadow data pointers are distinguished.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 INTERRUPT SYSTEM The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 provide 12 interrupt sources with three priority levels. The power management interrupt is at the highest priority level. The other two priority levels are configurable through the interrupt priority SFR (IP, Address 0xB8) and the interrupt enable and Priority 2 SFR (IEIP2, Address 0xA9).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 79. Interrupt Priority SFR (IP, Address 0xB8) Bit 7 6 5 4 3 2 1 0 Bit Address 0xBF 0xBE 0xBD 0xBC 0xBB 0xBA 0xB9 0xB8 Mnemonic PADE PTEMP PT2 PS PT1 PX1 PT0 PX0 Description ADE energy measurement interrupt Priority (1 = high, 0 = low). Temperature ADC interrupt priority (1 = high, 0 = low). Timer 2 interrupt priority (1 = high, 0 = low). UART serial port interrupt priority (1 = high, 0 = low). Timer 1 interrupt priority (1 = high, 0 = low).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 INTERRUPT FLAGS The interrupt flags and status flags associated with the interrupt vectors are shown in Table 82 and Table 83. Most of the interrupts have flags associated with them. Table 82. Interrupt Flags Interrupt Source IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 ITEMP (Temperature ADC) 1 IPSM (Power Supply) IADE (Energy Measurement DSP) 1 Flag TCON.1 TCON.5 TCON.3 TCON.7 SCON.1 SCON.0 T2CON.7 T2CON.6 N/A IPSMF.6 MIRQSTL.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 IE/IEIP2 REGISTERS PSM RTC ADE WATCHDOG TEMP ADC* IP/IEIP2 REGISTERS PRIORITY LEVEL LOW IPSMF HIGH HIGHEST FPSM (IPSMF.6) IPSME IN OUT LATCH RESET MIDNIGHT ALARM MIRQSTH MIRQSTM MIRQSTL MIRQENH MIRQENM MIRQENL MIRQSTL.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 INTERRUPT VECTORS CONTEXT SAVING When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off the stack by an RETI instruction. This allows program execution to resume from where it was interrupted. The interrupt vector addresses are shown in Table 84.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by default with a timeout of two seconds and creates a system reset if not cleared within two seconds.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 86. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA) Bit 7 Mnemonic WDPROT_PROTKY7 Default 1 [6:0] PROTKY[6:0] 0xFF Description This bit holds the protection for the watchdog timer and the seventh bit of the flash protection key. When this bit is cleared, the watchdog enable and event bits WDE and WDIR cannot be changed by user code. The watchdog configuration is then fixed to WDIR = 0 and WDE = 1.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 LCD DRIVER Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without compromising any ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 functions. It is capable of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD waveform voltages generated through internal charge pump circuitry support up to 5 V LCDs for the ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 89. LCD Configuration X SFR (LCDCONX, Address 0x9C) Bit 7 6 Mnemonic Reserved EXTRES Default 0 0 [5:0] BIASLV 0 1 Description Reserved. External resistor ladder selection bit. EXTRES Result 0 External resistor ladder is disabled. Charge pump is enabled. 1 External resistor ladder is enabled. Charge pump is disabled. Bias level selection bits. See Table 90.1 This feature is not available in the ADE7116. Table 90.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 93. LCD Frame Rate Selection for fLCDCLK = 2048 Hz (LCDCON[3] = 0) FD3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 FD2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 FD1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 FD0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 2× Multiplexing fLCD (Hz) Frame Rate (Hz) 256 128 1 170.7 85.3 128 64 102.4 51.2 85.3 42.7 73.1 36.6 64 32 56.9 28.5 51.2 25.6 46.5 23.25 42.7 21.35 39.4 19.7 36.6 18.3 34.1 17.05 32 16 16 8 3× Multiplexing fLCD (Hz) Frame Rate (Hz) 341.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 95. LCD Segment Enable SFR (LCDSEGE, Address 0x97) Bit 7 6 5 4 3 2 [1:0] Mnemonic FP25EN FP24EN FP23EN FP22EN FP21EN FP20EN Reserved Default 0 0 0 0 0 0 0 Description FP25 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP24 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP23 function select bit. 0 = general-purpose I/O, 1 = LCD function. FP22 function select bit. 0 = general-purpose I/O, 1 = LCD function.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The LCD waveform frequency, fLCD, is the frequency at which the LCD switches the active common line. Thus, the LCD waveform frequency depends heavily on the multiplex level. The frame rate and LCD waveform frequency are set by fLCDCLK, the multiplex level, and the FD[3:0] frame rate selection bits in the LCD clock SFR (LCDCLK, Address 0x96).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 99.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 LCD EXTERNAL CIRCUITRY LCD FUNCTION IN PSM2 MODE The voltage generation selection is made by the EXTRES bit (Bit 6) in the LCD configuration X SFR (LCDCONX, Address 0x9C). This bit is cleared by default for charge pump voltage generation, but it can be set to enable an external resistor ladder. The LCDPSM2 (Bit 4) and LCDEN (Bit 7) in the LCD configuration SFR (LCDCON, Address 0x95) control the LCD functionality in the PSM2 operating mode (see Table 100).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The LCD is set up with the following 8052 code: ; set up LCD pins to have LCD functionality MOV LCDSEG,#FP20EN+FP21EN+FP22EN+FP23EN MOV LCDSEGX,#FP16EN+FP17EN+FP18EN+FP19EN ; set up LCDCON for fLCDCLK=2048Hz, 1/3 bias and 4x multiplexing MOV LCDCON,#BIAS+LMUX1+LMUX0 ; setup LCDCONX for charge pump and BIASLVL[110111] MOV LCDCONX,#BIASLVL5+BIASLVL4+BIASLVL3+BIASLVL2+BIASLVL1+BIASLVL0 ; set up refresh rate for 64Hz with fLCDCLK=2048Hz MOV LCDCLK,#FD3+FD
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 FLASH MEMORY FLASH MEMORY OVERVIEW Flash memory is a type of nonvolatile memory that is in-circuit programmable. The default, erased state of a byte of flash memory is 0xFF. When a byte of flash memory is programmed, the required bits change from 1 to 0. The flash memory must be erased to turn the 0s back to 1s. A byte of flash memory cannot, however, be erased individually. The entire segment, or page, of flash memory that contains the byte must be erased.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 FLASH MEMORY ORGANIZATION The 16 kB array of flash memory provided by the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 are segmented into 32 pages of 512 bytes each. It is up to the user to decide which flash memory is to be used for data memory.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ECON COMMAND ADDRESS DECODER FLASH PROTECTION KEY FLSHKY PROTECTION DECODER ACCESS ALLOWED? TRUE: ACCESS ALLOWED ECON = 0 FALSE: ACCESS DENIED ECON = 1 FLSHKY = 0 × 3B? 06353-069 ADDRESS EADRH EADRL Figure 95. Flash Memory Read/Write/Erase Protection Block Diagram ECON—Flash Control SFR Programming flash memory is done through the Flash Control SFR (ECON, Address 0xB9).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 106. Flash Write/Erase Protection 0 SFR (PROTB0, Address 0xBD) Bit [7:0] Mnemonic PROTB0 Default 0xFF Description This SFR is used to write the write/erase protection bits for Page 0 to Page 7 of the flash memory (see the Protecting the Flash section). Clearing the bits enables the protection. PROTB0.7 PROTB0.6 PROTB0.5 PROTB0.4 PROTB0.3 PROTB0.2 PROTB0.1 PROTB0.0 Page 7 Page 6 Page 5 Page 4 Page 3 Page 2 Page 1 Page 0 Table 107.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Erase All Erase Page and Write Byte Erase all of the 16 kB flash memory. MOV FLSHKY,#3Bh key. ; Write Flash security Erase the page containing flash memory byte 0x3C00 and then write 0xF3 to that address. Note that the other 511 bytes in this page are erased. MOV ECON,#03h ; Erase all MOV EDATA,#F3h ; Data to be written Read Byte MOV EADRH,#3Ch ; Set up byte address Read flash memory byte 0x3C00.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 PROTECTING THE FLASH MEMORY The sequence for writing the flash protection follows: Two forms of protection are offered for this flash memory: read protection and write/erase protection. The read protection ensures that any pages that are read protected cannot be read by the end user. The write protection ensures that the flash memory cannot be erased or written over.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Enabling Flash Protection by Emulator Commands Another way to set the flash protection bytes is to use the reserved emulator commands available only in download mode. These commands write directly to the SFRs and can be used to duplicate the operation described in the Enabling Flash Protection by Code section. When these flash bytes are written, the part can exit emulation mode by reset and the protections are effective.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 TIMERS Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has three 16-bit timer/counters: Timer/Counter 0, Timer/Counter 1, and Timer/Counter 2. The timer/counter hardware is included on-chip to relieve the processor core of overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx (x = 0, 1, or 2). All three timers can be configured to operate as timers or as event counters.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 114. Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON, Address 0x88) Bit 7 Bit Address 0x8F Mnemonic TF1 Default 0 6 0x8E TR1 0 5 0x8D TF0 0 4 0x8C TR0 0 3 0x8B IE1 1 0 2 0x8A IT11 0 1 0x89 IE01 0 0 0x88 IT01 0 1 Description Timer 1 overflow flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the program counter (PC) vectors to the interrupt service routine. Timer 1 run control bit.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 116. Timer 0 High Byte SFR (TH0, Address 0x8C) Mode 0 (13-Bit Timer/Counter) Bit [7:0] Mode 0 configures an 8-bit timer/counter. Figure 97 shows Mode 0 operation. Note that the divide-by-12 prescaler is not present on the single-cycle core. Default 0 Description Timer 0 data high byte. Table 117. Timer 0 Low Byte SFR (TL0, Address 0x8A) Bit [7:0] Mnemonic TL0 Default 0 fCORE Description Timer 0 data low byte.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Mode 2 (8-Bit Timer/Counter with Autoreload) TIMER 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload as shown in Figure 99. Overflow from TL0 not only sets TF0 but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. Timer/Counter 2 Data Registers fCORE C/T = 0 INTERRUPT TL0 (8 BITS) TF0 C/T = 1 Timer/Counter 2 Operating Modes P0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 In either case, if Timer 2 is used to generate the baud rate, the TF2 interrupt flag does not occur. Therefore, Timer 2 interrupts do not occur and do not have to be disabled. In this mode, the EXF2 flag fCORE can, however, still cause interrupts that can be used as a third external interrupt. Baud rate generation is described as part of the UART serial port operation in the UART Serial Interface section.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 PLL The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple of this frequency to provide a stable 4.096 MHz clock for the system. The core can operate at this frequency or at binary submultiples of it to allow power savings when maximum core performance is not required. The default core clock is the PLL clock divided by 4, or 1.024 MHz.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 REAL-TIME CLOCK (RTC) The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have an embedded real-time clock (RTC) as shown in Figure 103. The external 32.768 kHz crystal is used as the clock source for the RTC. Calibration is provided to compensate the nominal crystal frequency and for variations in the external crystal frequency over temperature. By default, the RTC is maintained active in all power saving modes.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 128. RTC Configuration SFR (TIMECON, Address 0xA1) Bit 7 Mnemonic MIDNIGHT Default 0 6 TFH 0 [5:4] ITS 0 3 SIT 0 2 ALARM 0 1 ITEN 0 0 Reserved 1 Description Midnight flag. This bit is set when the RTC rolls over to 00:00:00:00. It can be cleared by the user to indicate that the midnight event has been serviced. In twenty-four hour mode, the midnight flag is raised once a day at midnight.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 133. RTC Alarm Interval SFR (INTVAL, Address 0xA6) Bit [7:0] Mnemonic INTVAL Default 0 Description The interval timer counts according to the time base established in the ITS bits of the RTC configuration SFR (TIMECON, 0xA1). When the number of counts is equal to INTVAL, the ALARM flag is set and a pending RTC interrupt is created. Note that the interval counter is eight bits. Therefore, it can count up to 255 seconds, for example. Table 134.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 READ AND WRITE OPERATIONS RTC MODES Writing to the RTC Registers The RTC can be configured in a 24-hour mode or a 256-hour mode. A midnight event is generated when the RTC hour counter rolls over from 23 to 0 or 255 to 0, depending on whether the TFH bit is set in the RTC Configuration SFR (TIMECON, Address 0xA1). The midnight event sets the MIDNIGHT flag in the TIMECON SFR, and a pending RTC interrupt is created.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Take care when changing the interval timer time base. The recommended procedure is as follows: 1. 2. 3. 4. If the alarm interval SFR (INTVAL, Address 0xA6) is going to be modified, write to this register first. Then, wait for one 128 Hz clock cycle to synchronize with the RTC, 64,000 cycles at a 4.096 MHz instruction cycle clock. Disable the interval timer by clearing the ITEN bit in the RTC configuration SFR (TIMECON, Address 0xA1).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 UART SERIAL INTERFACE The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 UART can be configured in one of four modes. (P1.0/RxD) and TxD (P1.1/TxD) pins, and the firmware interface is through the SFRs presented in Table 139. • • • • Both the serial port receive and transmit registers are accessed through the serial port buffer SFR (SBUF, Address 0x99).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 141. Serial Port Buffer SFR (SBUF, Address 0x99) Bit [7:0] Mnemonic SBUF Default 0 Description Serial port data buffer. Table 142. Enhanced Serial Baud Rate Control SFR (SBAUDT, Address 0x9E) Bit 7 Mnemonic OWE Default 0 6 FE 0 5 BE 0 [4:3] [2:0] SBTH DIV 0 0 Description Overwrite error. This bit is set when new data is received and RI = 1 (Bit 0 in the SCON SFR, Address 0x98).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 144. Common Baud Rates Using UART Timer with a 4.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 All of the following conditions must be met at the time the final shift pulse is generated to receive a character: UART OPERATION MODES Mode 0 (Shift Register with Baud Rate Fixed at fCORE/12) Mode 0 is selected when the SM0 and SM1 bits in the serial communications control register SFR (SCON, Address 0x98) are cleared. In this shift register mode, serial data enters and exits through the RxD pin. TxD outputs the shift clock.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 To transmit, the eight data bits must be written into the serial port buffer SFR (SBUF, Address 0x99). The ninth bit must be written to TB8 (Bit 3) in the serial communications control Register Bit Description SFR (SCON, 0x98). When transmission is initiated, the eight data bits from SBUF are loaded into the transmit shift register (LSB first). The ninth data bit, held in TB8, is loaded into the ninth bit position of the transmit shift register.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible. Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in Timer/Counter 2 control SFR (T2CON, Address 0xC8). The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 107.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 SBAUDF is the fractional divider ratio required to achieve the required baud rate. The appropriate value for SBAUDF can be calculated with the following formula: D2 D3 D4 D5 D6 D7 STOP D8 STOP Figure 108. UART Timing in Mode 1 Rx START D0 D1 D2 D3 D4 D5 D6 D7 RI SBAUDF ⎞ × ⎛⎜1 + ⎟ 64 ⎝ ⎠ 06353-083 16 × 2 D1 FE EXTEN = 1 f CORE DIV + SBTH D0 RI Note that SBAUDF should be rounded to the nearest integer.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 SERIAL PERIPHERAL INTERFACE (SPI) (P0.7/SS/T1) pins, while the firmware interface is via the SPI Configuration SFR 1 (SPIMOD1, Address 0xE8), the SPI Configuration SFR 2 (SPIMOD2, Address 0xE9), the SPI interrupt status SFR (SPISTAT, Address 0xEA), the SPI/I2C transmit buffer SFR (SPI2CTx, Address 0x9A), and the SPI/I2C receive buffer SFR (SPI2CRx, Address 0x9B).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 148. SPI Configuration SFR 1 (SPIMOD1, Address 0xE8) Bit [7:6] Mnemonic Reserved Default 0 Description Reserved. 5 Address 0xEF to 0xEE 0xED INTMOD 0 4 0xEC AUTO_SS 1 SPI interrupt mode. INTMOD Result 0 SPI interrupt is set when the SPI Rx buffer is full. 1 SPI interrupt is set when the SPI Tx buffer is empty. Master mode, SS output control (see Figure 110).
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 149. SPI Configuration SFR 2 (SPIMOD2, Address 0xE9) Bit 7 Mnemonic SPICONT Default 0 Description Master mode, SPI continuous transfer mode enable bit. SPICONT Result 0 The SPI interface stops after one byte is transferred and SS is deasserted. A new data transfer can be initiated after a stalled period. 1 The SPI interface continues to transfer data until no valid data is available in the SPI2CTx SFR.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 150. SPI Interrupt Status SFR (SPISTAT, Address 0xEA) Bit 7 Mnemonic BUSY Default 0 6 MMERR 0 5 SPIRxOF 0 4 SPIRxIRQ 0 3 2 SPIRxBF SPITxUF 0 0 1 SPITxIRQ 0 0 SPITxBF 0 Description SPI peripheral busy flag. BUSY Result 0 The SPI peripheral is idle. 1 The SPI peripheral is busy transferring data in slave or master mode. SPI multimaster error flag. MMERR Result 0 A multiple master error has not occurred.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 In both master and slave modes, the data is transmitted on one edge of the SCLK signal and sampled on the other. It is important, therefore, that the SPICPHA and SPICPOL bits be configured the same for the master and slave devices. SS (Slave Select Pin) In SPI slave mode, a transfer is initiated by the assertion of SS low.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The SPI interface has several status flags that indicate the status of the double-buffered receive and transmit registers. Figure 111 shows when the status and interrupt flags are raised. The transmit interrupt occurs when the internal serial port shift register is loaded with the data in the SPI/I2C transmit buffer SFR (SPI2CTx, Address 0x9A) register.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 I2C-COMPATIBLE INTERFACE The bit rate is defined in the I2CMOD SFR as follows: The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 support a fully licensed I2C interface. The I2C interface is implemented as a full hardware master. f SCLK = SDATA (P0.4/MOSI/SDATA) is the data I/O pin, and SCLK (P0.6/SCLK/T0) is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on-chip SPI interface.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 154. I2C Interrupt Status Register SFR (SPI2CSTAT, Address 0xEA) Bit 7 6 Mnemonic I2CBUSY I2CNOACK Default 0 0 5 I2CRxIRQ 0 4 I2CTxIRQ 0 [3:2] I2CFIFOSTAT 0 1 0 I2CACC_ERR I2CTxWR_ERR 0 0 Description This bit is set to Logic 1 when the I2C interface is used. When set, the Tx FIFO is emptied. I2C no acknowledgement transmit interrupt. This bit is set to Logic 1 when the slave device does not send an acknowledgement.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 The I2C peripheral has a 4-byte receive FIFO and a 4-byte transmit FIFO. The buffers reduce the overhead associated with using the I2C peripheral. Figure 115 shows the operation of the I2C receive and transmit FIFOs. The Tx FIFO can be loaded with four bytes to be transmitted to the slave at the beginning of a write operation.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 I/O PORTS PARALLEL I/O Weak Internal Pull-Ups Enabled The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 use three input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of driving an LCD or performing alternate functions for the peripherals available on-chip. In general, when a peripheral is enabled, the pins associated with it cannot be used as a general-purpose I/O.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 I/O REGISTERS Table 156. Extended Port Configuration SFR (EPCFG, Address 0x9F) Bit 7 6 5 4 3 2 1 0 Mnemonic MOD38_FP21 MOD38_FP22 MOD38_FP23 MOD38_TxD MOD38_CF1 MOD38_SSb MOD38_MISO MOD38_CF2 Default 0 0 0 0 0 0 0 0 Description This bit enables 38 kHz modulation on the P1.6/FP21 pin. This bit enables 38 kHz modulation on the P1.5/FP22 pin. This bit enables 38 kHz modulation on the P1.4/T2/FP23 pin. This bit enables 38 kHz modulation on the P1.1/TxD pin.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 160. Port 0 SFR (P0, Address 0x80) Bit 7 6 5 4 3 2 1 0 1 Bit Address 0x87 0x86 0x85 0x84 0x83 0x82 0x81 0x80 Mnemonic T1 T0 CF2 CF1 INT1 Default 1 1 1 1 1 1 1 1 Description 1 This bit reflects the state of the P0.7/SS/T1 pin. It can be written to or read. This bit reflects the state of the P0.6/SCLK/T0 pin. It can be written to or read. This bit reflects the state of the P0.5/MISO pin. It can be written to or read.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Table 163. Port 0 Alternate Functions Pin No. P0.0 Alternate Function BCTRL external battery control input INT1 external interrupt INT1 wake-up from PSM2 operating mode P0.1 P0.2 FP19 LCD segment pin CF1 ADE calibration frequency output P0.3 CF2 ADE calibration frequency output P0.4 MOSI SPI data line SDATA I2C data line P0.5 MISO SPI data line P0.6 SCLK serial clock for I2C or SPI T0 Timer 0 input P0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 PORT 0 Port 0 is controlled directly through the bit-addressable Port 0 SFR (P0, Address 0x80). The weak internal pull-ups for Port 0 are configured through the Port 0 weak pull-up Enable SFR (PINMAP0, Address 0xB2); they are enabled by default. The weak internal pull-up is disabled by writing a 1 to PINMAP0.x. Port 0 pins also have various secondary functions, as described in Table 163.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 DETERMINING THE VERSION OF THE PART Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 holds in its internal flash registers a value that defines its version. This value helps to determine whether users have the latest version of the part. The version of the ADE7116/ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 that corresponds to this data sheet is ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 V3.4. This value can be accessed as follows: 1. 2. 3. 4.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° SEATING PLANE 16 33 32 17 0.08 COPLANARITY VIEW A VIEW A 0.27 0.22 0.17 0.50 BSC LEAD PITCH 051706-A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 118. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters 9.00 BSC SQ 0.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 ORDERING GUIDE Model 1 ADE7116ASTZF16 2 , 3 , 4 ADE7116ASTZF16-RL2, 3, 4 ADE7116ASTZF82, 3, 4 ADE7116ASTZF8-RL2, 3, 4 ADE7156ASTZF162, 4 ADE7156ASTZF16-RL2, 4 ADE7156ASTZF82, 4 ADE7156ASTZF8-RL2, 4 ADE7166ACPZF82 ADE7166ACPZF8-RL2 ADE7166ACPZF162 ADE7166ACPZF16-RL2 ADE7166ASTZF82 ADE7166ASTZF8-RL2 ADE7166ASTZF162 ADE7166ASTZF16-RL2 ADE7169ACPZF162 ADE7169ACPZF16-RL2 ADE7169ASTZF82 ADE7169ASTZF8-RL2 ADE7169ASTZF162 ADE7169ASTZF16-RL2 ADE7566ACPZF82 ADE7566ACPZF
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 NOTES Rev.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 NOTES Rev.
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.