Datasheet

ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 54 of 156
–89.75
–89.80
–89.85
–89.90
–89.95
–90.00
FREQUENCY (Hz)
PHASE (Degrees)
40 45 7050 55 60 65
–90.05
–89.70
07411-030
Figure 54. Combined Phase Response of the Digital Integrator and
Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a −20 dB/dec attenuation and an
approximately −90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be
a flat gain over the frequency band of interest. The di/dt sensor
has a 20 dB/dec gain associated with it. It also generates significant
high frequency noise. Therefore, a more effective antialiasing
filter is needed to avoid noise due to aliasing (see the Antialiasing
Filter section).
When the digital integrator is switched off, the ADE5169/ADE5569
can be used directly with a conventional current sensor, such as a
current transformer (CT), or with a low resistance current shunt.
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
Each ADE5166/ADE5169/ADE5566/ADE5569 has a zero-
crossing detection circuit on the voltage channel. This external
zero-crossing signal can be output on P0.5 and P1.2 (see Table 39).
It is also used in calibration mode.
The zero crossing is generated by default from the output of LPF1.
This filter has a low cutoff frequency and is intended for 50 Hz
and 60 Hz systems. If needed, this filter can be disabled to allow
a higher frequency signal to be detected or to limit the group delay
of the detection. If the voltage input fundamental frequency is
below 60 Hz, and a time delay in ZX detection is acceptable, it
is recommended that LPF1 be enabled. Enabling LPF1 limits the
variability in the ZX detection by eliminating the high frequency
components. Figure 55 shows how the zero-crossing signal is
generated.
The zero-crossing signal, ZX, is generated from the output of
LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at
MCLK = 4.096 MHz). As a result, there is a phase lag between
the analog input signal, V2, and the output of LPF1. The phase
lag response of LPF1 results in a time delay of approximately
2 ms (at 60 Hz) between the zero crossing on the analog inputs
of the voltage channel and ZX detection.
×1, ×2, ×4,
×8, ×16
ADC 2
REFERENCE
LPF1
f
–3dB
= 63.7Hz
PGA2
{GAIN[7:5]}
V
P
V
N
V2
ZERO
CROSSING
ZX
HPF
MODE1[6]
43.24° @ 60Hz
1.0
0.73
ZX
V2
LPF1
07411-031
Figure 55. Zero-Crossing Detection on the Voltage Channel
The zero-crossing detection also drives the ZX flag in the Inter-
rupt Status 3 SFR (MIRQSTH, Address 0xDE). If the ZX bit (Bit 0)
in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set,
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the ZX status bit is cleared (see the Energy
Measurement Interrupts section).
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout
register, ZXTOUT. This unsigned, 12-bit register is decremented
(1 LSB) every 160/MCLK sec. The register is reset to its user-
programmed, full-scale value every time a zero crossing is detected
on the voltage channel. The default power-on value in this register
is 0xFFF. If the internal register decrements to 0 before a zero
crossing is detected in the Interrupt Status 3 SFR (MIRQSTH,
Address 0xDE) and the ZXTO bit (Bit 1) in the Interrupt Enable 3
SFR (MIRQENH, Address 0xDB) is set, the 8052 core has a
pending ADE interrupt.
The ADE interrupt stays active until the ZXTO status bit is
cleared (see the Energy Measurement Interrupts section). The
ZXTOUT register (Address 0x11) can be written to or read by
the user (see the Energy Measurement Registers section). The
resolution of the register is 160/MCLK sec per LSB. Thus, the
maximum delay for an interrupt is 0.16 sec (1/MCLK × 2
12
) when
MCLK = 4.096 MHz.